• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.2
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• pp.106-109
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• 2004

A high-density 3-transistor cell one-time programmable (OTP) ROM array using standard CMOS Gate-Oxide antifuse (AF) is proposed, fabricated, and characterized with $0.18{\mu}m$ CMOS process. The proposed non-volatile high-density OTP ROM is composed of an array of 3-T OTP cells with the 3-T consisting of an nMOS AF, a high voltage (HV) blocking transistor, and a cell access transistor, all compatible with standard CMOS technology.

• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2327-2329
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• 1998

In this paper, an algorithm to make a configuration system for managing the I/O device of programmable logic controller(PLC) is proposed. Parallel processing architecture is used to deal with a number of I/O devices. From that architecture, a contention problem between processors can arise. To resolve this problem, the configuration system that contains informations about I/O devices is introduced. This configuration system is used to check the contention between processors in the I/O device and also used in program execution.

• Proceedings of the KIEE Conference
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• 2005.10a
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• pp.180-183
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• 2005

A programmable dynamometer is the proposed system improved the problem of the torque measuring delay with torque transducer, and the load torque is estimated by the minimal order state observer based on the torque component of the vector control induction moter. Therefore, the torque controller is not affected by a load torque disturbance. To verify a superiority of the proposed control algorithm, the analysis for a root locus of a conventional control method and the proposed one, and simulation and experiment is performed. Therefore we hope to be extended in industrial application.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.5
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• pp.492-504
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• 1987

The Binary Decision method can evaluate any switching function in the number of steps not exceeding the number of input variables. A Binary Decision Programmable Controller module is designed using this method so as to improve scan speed. A compiler system is also developed to relieve the memory problem which the Binary Decision method entails. A communication channel between MDS and BD-PC modules is also constructed to load the compiled BD-PC object program into the memory of BD machine.

• ETRI Journal
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• v.37 no.4
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• pp.787-792
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• 2015

To accomplish a high-speed test on low-speed automatic test equipment (ATE), a new instruction-based fully programmable memory built-in self-test (BIST) is proposed. The proposed memory BIST generates a highspeed internal clock signal by multiplying an external low-speed clock signal from an ATE by a clock multiplier embedded in a DRAM. For maximum programmability and small area overhead, the proposed memory BIST stores the unique sets of instructions and corresponding test sequences that are implicit within the test algorithms that it receives from an external ATE. The proposed memory BIST is managed by an external ATE on-the-fly to perform complicated and hard-to-implement functions, such as loop operations and refresh-interrupts. Therefore, the proposed memory BIST has a simple hardware structure compared to conventional memory BIST schemes. The proposed memory BIST is a practical test solution for reducing the overall test cost for the mass production of commodity DDRx SDRAMs.

• Journal of Institute of Control, Robotics and Systems
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• v.7 no.12
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• pp.1009-1014
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• 2001

The ladder diagram (LD) for programmable logic controllers (PLCs) ar responsible for much important roles in advance industrial automation. As automated systems become more complex the design procedures of the system become more difficult as well. Hence. the design automation issues based on discrete event models(DEMs) are receiving more attention. One of the popular ways of tackling these problems is employing Petri nets. In this paper, we use the modified automation Petri net(MAPN) to model the manufacturing system and the modified token passing logic (MTPL) method conversion (ECC) algorithm based on the MAPN and the MTPL Finally, an example of the manufacturing system is provided to illustrate the proposed ECC algorithm.

• Journal of the Korean Institute of Telematics and Electronics
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• v.10 no.5
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• pp.1-6
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• 1973

The paper deals with a study on an electronic watering device. The system is designed to scan 10 probes so that they detect moisture of soil. Input potentials are compared with reference level before the system is watering. rt provides a main clock oscillator and a control oscillator for the system control, and a programmable unijunction transistor is used for the control circuit. The reference levels are adjustable so as to water various soils. The device is tested for two different sails of moisture content ranging from 6 to 51%. It works at any input level higher than 0.6 V compared to the reference level.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.4
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• pp.16-23
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• 1983

A programmable controller (PC) which can control general sequential process is developed. The Z-8OA microprocessor-based PC includes hardwares such as programming device, input/output modules, timer/counter modules, and power-failure recovery module which for soft-ware, initialization program, monitor program, execution program, and power-failure recovery program are developed. In particular, the PC is designed in such a way that a timer can be used several times in different time intervals and a skip capability is incorporated in the user program to reduce scan time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.999-1007
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• 2002

In this paper, the operation of matched filter for searching initial synchronization in direct sequence spread spectrum receiver is studied. The implementation model of the matched filter by HDL (Hardware Description Language) is proposed. The model has an architecture based on parallelism and pipeline for fast processing, which includes circular buffer, multiplier, adder, and code look-up table. The performance of the model is analyzed and compared with the implementation by a conventional digital signal processor. It is implemented on a FPGA (Field Programmable Gate Array) and its operation is validated in a timing simulation result.

• Journal of Power Electronics
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• v.6 no.2
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• pp.114-120
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• 2006

This paper compares two types of direct torque controllers for permanent magnet synchronous motors(PMSMs). These controllers both use a single-chip FPGA(Field Programmable Gate Array) but have differing hardware configurations. One of the controllers was constructed by programming a soft-core CPU and hardware logic circuits written in VHDL(Very high speed IC Hardware Description Language), while the other was constructed of only hardware logic circuits. The characteristics of these two controllers were compared in this paper. The results show the controller constructed of only hardware logic circuits was able to shorten the control period and it was able to suppress the low torque ripple.