• The Journal of the Acoustical Society of Korea
• /
• v.25 no.1E
• /
• pp.20-24
• /
• 2006

In this paper, we focused on the real time implementation of a speech recognition system with medium size of vocabulary considering its application to a mobile phone. First, we developed the PC based variable vocabulary word recognizer having the size of program memory and total acoustic models as small as possible. To reduce the memory size of acoustic models, linear discriminant analysis and phonetic tied mixture were applied in the feature selection process and training HMMs, respectively. In addition, state based Gaussian selection method with the real time cepstral normalization was used for reduction of computational load and robust recognition. Then, we verified the real-time operation of the implemented recognition system on the TMS320C6201 EVM board. The implemented recognition system uses memory size of about 610 kbytes including both program memory and data memory. The recognition rate was 95.86% for ETRI 445DB, and 96.4%, 97.92%, 87.04% for three kinds of name databases collected through the mobile phones.

• Journal of Information Processing Systems
• /
• v.17 no.1
• /
• pp.191-202
• /
• 2021

In an Internet of Things (IoT)-configured system, each device executes on-chip software. Recent IoT devices require fast execution time of complex services, such as analyzing a large amount of data, while maintaining low-power computation. As service complexity increases, the service requires high-performance computing and more space for embedded space. However, the low performance of IoT edge devices and their small memory size can hinder the complex and diverse operations of IoT services. In this paper, we propose a remote on-demand software code execution unit using the cloudification of on-chip code memory to accelerate the program execution of an IoT edge device with a low-performance processor. We propose a simulation approach to distribute remote code executed on the server side and on the edge side according to the program's computational and communicational needs. Our on-demand remote code execution unit simulation platform, which includes an instruction set simulator based on 16-bit ARM Thumb instruction set architecture, successfully emulates the architectural behavior of on-chip flash memory, enabling embedded devices to accelerate and execute software using remote execution code in the IoT environment.

• The Journal of Korean Association of Computer Education
• /
• v.15 no.3
• /
• pp.37-47
• /
• 2012

One of the major goals in high school Informatics is for students to develop creative problem-solving abilities based on knowledge on computer science. Thus, the contents of the textbooks should be accurate and appropriate. However, we discovered that the current Informatics textbooks contain the untrue and/or inappropriate descriptions of main memory and virtual memory. The textbooks describe that main memory is composed of RAM and ROM. The virtual memory is described as a technique in which a part of the secondary storage is utilized as main memory to execute an application of which size is larger than that of main memory. In this study, we attempted to uncover the root causes of the fallacies, and suggest the accurate explanations by comparing with renowned books adopted in most schools worldwide including USA. Our study reveals that it is inappropriate to include ROM in main memory from the memory hierarchy perspective. Virtual memory is a technique that provides convenience to programmers, through which an operating system loads the necessary portion of a program from secondary storage to main memory. As for the advantages of virtual memory in the current computer systems, the focus should be on providing the effective multitasking capability, rather than on executing a larger program than the size of main memory. We suggest that it is appropriate to exclude virtual memory in textbooks considering its complexity.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.2
• /
• pp.286-291
• /
• 2015

For highly scalable NAND flash memory applications, a compact ($4F^2/cell$) nonvolatile memory architecture is proposed and investigated via three-dimensional device simulations. The back-channel program/erase is conducted independently from the front-channel read operation as information is stored in the form of charge at the backside of the channel, and hence, read disturbance is avoided. The memory cell structure is essentially equivalent to that of the fully-depleted transistor, which allows a high cell read current and a steep subthreshold slope, to enable lower voltage operation in comparison with conventional NAND flash devices. To minimize memory cell disturbance during programming, a charge depletion method using appropriate biasing of a buried back-gate line that runs parallel to the bit line is introduced. This design is a new candidate for scaling NAND flash memory to sub-20 nm lateral dimensions.

• Journal of the Korea Society of Computer and Information
• /
• v.11 no.6 s.44
• /
• pp.113-123
• /
• 2006

Flash memory has been increasingly used in handhold devices not only for data storage, but also for code storage. Because NAND flash memory only provides sequential access feature, a traditionally accepted solution to execute the program from NAND flash memory is shadowing. But, shadowing has significant drawbacks increasing a booting time of the system and consuming severe DRAM space. Demand paging has obtained significant attention for program execution from NAND flash memory. But. one of the issues is that there has been no effort to bound demand paging cost in flash memory and to analyze the worst case performance of demand paging. For the worst case timing analysis of programs running from NAND flash memory. the worst case demand paging costs should be estimated. In this paper, we propose two different WCRT analysis methods considering demand paging costs, DP-Pessimistic and DP-Accurate, depending on the accuracy and the complexity of analysis. Also, we compare the accuracy butween DP-Pessimistic and DP-Accurate by using the simulation.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.2
• /
• pp.317-326
• /
• 2016

In this paper, a logic eFuse (electrical Fuse) OTP (One-Time Programmable) memory IP (Intellectual Property) using only logic transistors to reduce the development cost and period of OTP memory IPs is designed. To secure the reliability of other IPs than the OTP memory IP, a higher voltage of 2,4V than VDD (=1.5V) is supplied to only eFuse links of eFuse OTP memory cells directly through an external pad FSOURCE coming from test equipment in testing wafers. Also, an eFuse OTP memory cell of which power is supplied through FSOURCE and hence the program power is increased in a two-dimensional memory array of 128 rows by 8 columns being also able to make the decoding logic implemented in small area. The layout size of the designed 1kb eFuse OTP memory IP with the Dongbu HiTek's 110nm CIS process is $295.595{\mu}m{\times}455.873{\mu}m$ ($=0.134mm^2$).

• Journal of Korean Public Health Nursing
• /
• v.32 no.1
• /
• pp.81-95
• /
• 2018

Purpose: This study was conducted to identify the effects of a group cognitive improvement program on cognitive function, depression and self-esteem in elderly individuals with mild cognitive impairment. Methods: This was an experimental study that employed a pre-post design of a non-equivalence control group. The subjects were 52 elderly people with mild cognitive impairment, 25 of whom were assigned to the experimental group and 27 to the control group. The program was conducted for a total of 12 sessions for 60 minutes each. Data were analyzed using the ${\chi}2-test$, Fisher's exact test, and Independent t-test with the SPSS 20.0 program. Results: After the intervention, the group who participated showed improvement in all areas of cognitive function based on MMSE-KC (F=26.37, p.<0.001), the Rey Complex Figure Test: copy (F=20.66, p.<0.001), Immediate memory of Seoul Verbal Learning Test-Elderly's version (F=29.68, p.<0.001), delayed memory (F=45.79 p.<0.001), memory recall (F=28.97, p.<0.001), Forward of Digit Span Test (F=9.25, p=.004), backward (F=8.33, p.=0.006), language comprehension (F=13.42, p.<0.001), and digit symbol coding (F=17.74, p.<0.001) relative to the control group. Moreover depression (F=24.09, p.<0.001) was decreased in program participants, whereas self-esteem (F=40.24, p.<0.001) was increased. Conclusion: The program could be a useful intervention because the results show that the group cognitive improvement program has a significant effect on cognitive function, depression and self-esteem in elderly with mild cognitive impairment.

• Proceedings of the KIEE Conference
• /
• 1999.07g
• /
• pp.3067-3069
• /
• 1999

In this paper, A bit processor for controlling sequence logic was implemented, using a FPGA. This processor consists of program memory interface. I/O interface, parts for instruction fetch and decode, registers, ALU, program counter and etc. This FPGA is able to execute sequence instruction during program fetch cycle, because of divided bus system, program bus and data bus. Also this bit processor has instructions set that 16bit or 32bit fixed width, so instruction decoding time and data memory interface time was reduced. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package. Finally, the benchmark was performed to prove that Our FPGA has better performance than DSP(TMS320C32-40MHz) for the sequence logic control of PLC.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.15 no.10
• /
• pp.2209-2216
• /
• 2011

In this paper, we design a 32-bit eFuse OTP memory for PMICs using MagnaChip's $0.18{\mu}m$ process. We solve a problem of an electrical shortage between an eFuse link and the VSS of a p-substrate in programming by placing an n-well under the eFuse link. Also, we propose a WL driver circuit which activates the RWL (read word-line) or WWL (write word-line) of a dual-port eFuse OTP memory cell selectively when a decoded WERP (WL enable for read or program) signal is inputted to the eFuse OTP memory directly. Furthermore, we reduce the layout area of the control circuit by removing a delay chain in the BL precharging circuit. We'can obtain an yield of 100% at a program voltage of 5.5V on 94 manufactured sample dies when measured with memory tester equipment.

• Journal of KIISE:Computing Practices and Letters
• /
• v.16 no.12
• /
• pp.1177-1187
• /
• 2010

Flash memory becomes popular storage for small devices due to its efficiency, portability, low power consumption and large capacity. Unlike on hard disks, however, write operation on flash memory is much more expensive than read operation, so that it is critical for performance enhancement to reduce the number of executions of write operation. This paper proposes static analysis to rewrite a program to reduce the total number of write operations by merging writable data in a minimum number of pages. To achieve this, we collect information about writable areas by static analysis, and about frequently executed paths by profiling for practicality, and combine both to rewrite the application program to reallocate data. The performance enhancement gained from the proposed methods is shown using a FAST simulator.