• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.24-38
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• 2009

In this paper, we implement processor debugger based on OCD(On-Chip Debugger). Implemented debugger consist of software debugger that supports a functionality of symbolic debugging, OCD integrated into target processor as a function of debugging, and Interface & Control block which interfaces software debugger and OCD at high speed rates. The debugger supports c/assembly level debugging using software debugger as OCD is integrated into target processor. After OCD block is interfaced with 32bit RISC processor core and then implemented with FPGA, the verification of On-Chip Debugging System is carried out through connecting OCD and Interface & Control block, and SW debugger.

• ETRI Journal
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• v.35 no.2
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• pp.301-310
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• 2013

Nowadays, the multicore processor is watched with interest by people all over the world. As the design technology of system on chip has developed, observing and controlling the processor core's internal state has not been easy. Therefore, multicore processor debugging is very difficult and time-consuming. Thus, we need a reliable and efficient debugger to find the bugs. In this paper, we propose an on-chip debug architecture for multicore processors that is easily adaptable and flexible. It is based on the JTAG standard and supports monitoring mode debugging, which is different from run-stop mode debugging. Compared with the debug architecture that supports the run-stop mode debugging, the proposed architecture is easily applied to a debugger and has the advantage of having a desirable gate count and execution cycle. To verify the on-chip debug architecture, it is applied to the debugger of the prototype multicore processor and is tested by interconnecting it with a software debugger based on GDB and configured for the target processor.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.329-332
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• 2002

The traditional debug tools for chip tests and software developments need a huge investment and a plenty of time. These problems can be overcome by Embedded Debugger based the JTAG boundary Scan Architecture. Thus, the IEEE 1149.1 standard is adopted by ASIC designers for the testability problems. We designed the RED(Reusable Embedded Debugger) using the JTAG boundary Scan Architecture. The proposed debugger is applicable for not a chip test but also a software debugging. Our debugger has an additional hardware module (EICEM : Embedded ICE Module) for more critical real-time debugging.

• ETRI Journal
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• v.34 no.1
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• pp.44-54
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• 2012

Because of the intrinsic lack of internal-system observability and controllability in highly integrated multicore processors, very restricted access is allowed for the debugging of erroneous chip behavior. Therefore, the building of an efficient debug function is an important consideration in the design of multicore processors. In this paper, we propose a flexible on-chip debug architecture that embeds a special logic supporting the debug functionality in the multicore processor. It is designed to support run-stop-type debug functions that can halt and control the execution of the multicore processor at breakpoint events and inspect the possible causes of any errors. The debug architecture consists of the following three functional components: the core debug support block, the multicore debug support block, and the debug interface and control block. By embedding this debug infrastructure, the embedded processor cores within the multicore processor can be debugged simultaneously as well as independently. The debug control is performed by employing a JTAG-based scanning operation. We apply this on-chip debug architecture to build a debugger for a prototype multicore processor and demonstrate the validity and scalability of our approach.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.65-75
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• 2011

As the technology of SoC design has been developed, the debugging is more and more important and users want a fast and reliable debugger. This paper deals with an implementation of the fast debugger which can reduce a debugging processing cycle by designing a modified JTAG suitable for a new RISC processor debugger. Designed JTAG is embedded to the OCD of Core-A and works with SW debugger. We confirmed the functions and reliability of the debugger. By comparing to the original JTAG system, the debugging processing cycle of the proposed JTAG is reduced at 8.5~72.2% by each debugging function. Further more, the gate count is reduced at 31.8%.

• Journal of Platform Technology
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• v.10 no.4
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• pp.62-69
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• 2022

Flight control systems installed on unmanned aircraft require thorough verification from the design stage. This verification is made through the integrated flight control test environment. Typically, a debugger is used to monitor the internal state of a flight control computer in real time. Emulator with a real-time memory monitor and trace is relatively expensive. The JTAG Emulator is unable to operate in real time and has limitations that cannot be caught up with the processing speed of latest high-speed processors. In this paper, we describe the results of the development of internal monitoring software for drone flight control computer processors based on NUTTX/PIXHAWK. The results of this study show that the functions provided compared to commercial debugger are limited, but it can be sufficiently used to verify the flight control system using this system under limited budget.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.50-61
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• 2010

Nowadays, the SoC is watched by all over the world with interest. The design trend of the SoC is hardware and software co-design which includes the design of hardware structure in RTL level and the development of embedded software. Also the technology is toward deep-submicron and the observability of the SoC's internal state is not easy. Because of the above reasons, the SoC debug is very difficult and time-consuming. So we need a reliable debugger to find the bugs in the SoC and embedded software. In this paper, we developed a hardware debugger named OCD. It is based on IEEE 1140.1 JTAG standard. In order to verify the operation of OCD, it is integrated into the 32bit RISC processor - Core-A (Core-A is the unique embedded processor designed by Korea) and is tested by interconnecting with software debugger. When embedding the OCD in Core-A, there is 14.7% gate count overhead. We can modify the DCU which occupies 2% gate count in OCD to adapt with other processors as a debugger.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.2
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• pp.83-88
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• 2015

Core-A is 32-bit synthesizable processor core with a unique instruction set architecture (ISA). In this paper, the Core-A ISA is introduced with discussion of useful features and the development environment, including the software tool chain and hardware on-chip debugger. Core-A is described using Verilog-HDL and can be customized for a given application and synthesized for an application-specific integrated circuit or field-programmable gate array target. Also, the GNU Compiler Collection has been ported to support Core-A, and various predesigned platforms are well equipped with the established design flow to speed up the hardware/software co-design for a Core-A-based system.

• Proceedings of the IEEK Conference
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• 2000.06c
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• pp.67-70
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• 2000

In a distributed real-time system(DRTS), testing and debugging are difficult and critical procedures since they implies several problems like probe effects, nondeterminism, and complex communication patterns. In this paper, we describe the design and implementation of a real-time monitor for ARM processors which are frequently used for embedded applications. The focus of design is to help users debug real-time programs while minimizing the probe effect. Our monitor provides cross debugging features like down-loading from host, break-point based debugging features, and watch-point debugging features for real-time applications. We developed the debugger for ARM processor and debugger has been used for kernel program.

• Proceedings of the Korean Information Science Society Conference
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• 2011.06b
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• pp.325-327
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• 2011

온보드 대상의 디버깅은 타깃머신의 처리 속도 및 통신 속도의 제약으로 인해 발생하는 지연시간 때문에 개발 기간이 길어지게 된다. 이런 문제를 해결하고자 소프트웨어 에뮬레이터를 상위 성능의 머신에서 구동하고 온보드로는 인스트럭션과 그에 필요한 데이터의 전송만 진행하여 온보드로부터의 메모리 전송을 최소화함으로써 지연시간을 감소시키는 효과를 얻을 수 있다. 본 논문에서는 Zaram사(社)의 CDSP16V2 프로세서를 위한 디버거 성능 개선 방법 및 구현에 대하여 서술한다.