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Design and Verification of Efficient On-Chip Debugger for Core-A  

Xu, Jingzhe (School of Electrical Engineering, Pusan National University)
Park, Hyung-Bae (School of Electrical Engineering, Pusan National University)
Jung, Seung-Pyo (School of Electrical Engineering, Pusan National University)
Park, Ju-Sung (School of Electrical Engineering, Pusan National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.47, no.4, 2010 , pp. 50-61 More about this Journal
Abstract
Nowadays, the SoC is watched by all over the world with interest. The design trend of the SoC is hardware and software co-design which includes the design of hardware structure in RTL level and the development of embedded software. Also the technology is toward deep-submicron and the observability of the SoC's internal state is not easy. Because of the above reasons, the SoC debug is very difficult and time-consuming. So we need a reliable debugger to find the bugs in the SoC and embedded software. In this paper, we developed a hardware debugger named OCD. It is based on IEEE 1140.1 JTAG standard. In order to verify the operation of OCD, it is integrated into the 32bit RISC processor - Core-A (Core-A is the unique embedded processor designed by Korea) and is tested by interconnecting with software debugger. When embedding the OCD in Core-A, there is 14.7% gate count overhead. We can modify the DCU which occupies 2% gate count in OCD to adapt with other processors as a debugger.
Keywords
JTAG; halt-mode debugging; Core-A;
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Times Cited By KSCI : 1  (Citation Analysis)
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