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Design of Modified JTAG for Debuggers of RISC Processors  

Xu, Jingzhe (Department of Electrical & Electronic Engineering, Pusan National University)
Park, Hyung-Bae (Department of Electrical & Electronic Engineering, Pusan National University)
Jung, Seung-Pyo (Department of Electrical & Electronic Engineering, Pusan National University)
Park, Ju-Sung (Department of Electrical & Electronic Engineering, Pusan National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.48, no.7, 2011 , pp. 65-75 More about this Journal
Abstract
As the technology of SoC design has been developed, the debugging is more and more important and users want a fast and reliable debugger. This paper deals with an implementation of the fast debugger which can reduce a debugging processing cycle by designing a modified JTAG suitable for a new RISC processor debugger. Designed JTAG is embedded to the OCD of Core-A and works with SW debugger. We confirmed the functions and reliability of the debugger. By comparing to the original JTAG system, the debugging processing cycle of the proposed JTAG is reduced at 8.5~72.2% by each debugging function. Further more, the gate count is reduced at 31.8%.
Keywords
JTAG; TAP block; On-Chip Debugger; Core-A; RISC processor;
Citations & Related Records
Times Cited By KSCI : 4  (Citation Analysis)
연도 인용수 순위
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