• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.4
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• pp.571-578
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• 2023

In this paper, we propose a low EMI data transmitter employing a delay-locked loop for vehicles. For the low EMI characteristic, the transmitter has been designed to have low slew rate and employs the delay-locked loop to correct the amount of change in the slew rate due to process variations. According to simulation results, the proposed transmitter which the delay-locked loop has smaller slew rate change as compared to the conventional transmitter. The proposed circuit has been designed with a 65nm process technology and the data rate is 20Mbps with a supply voltage of 1.1V. As compared to a conventional transmitter, the proposed transmitter shows that variations of the slew rate become 53.6% lower in a fast condition and 13.07% lower in a slow condition.

• Journal of Electrical Engineering and Technology
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• v.8 no.6
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• pp.1431-1438
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• 2013

A pack-level battery hardware-in-the-loop simulation (B-HILS) platform is implemented. It consists of dynamic vehicle models using PSAT and multiple control interfaces including real-time 3D driving and GPS mode. In real-time 3D driving mode, user can drive a virtual vehicle using actual drive equipment such as steering wheel and accelerator to generate the cycle profile of the battery. In GPS mode, actual road traffic and terrain effects can be simulated using GPS data while the trajectory is displayed on Google map. In the latter part of the paper, several performance tests of an actual lithium-polymer battery pack are carried out utilizing the developed system. All experiments are conducted as parts of actual development process of a commercial battery pack adopting 2nd generation Prius as a target vehicle model. Through the experiments, the low temperature performance and fuel efficiency of the battery are quantitatively investigated in comparison with the original nickel-metal hydride (NiMH) pack of the Prius.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.12
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• pp.2933-2938
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• 2014

In this paper, the FLL(Frequency Locked Loop) circuit using current conveyor circuit is designed by $0.35{\mu}m$ CMOS process. The FLL circuit is built in a frequency divider, a frequency-to-voltage converter, a voltage subtractor and a oscillator and the circuit blocks have a symmetric structure to improve a reliability characteristics with a process variation. From the simulation results, the variation rate of output frequency is about less than ${\pm}1%$ when the channel length, channel width, resistance and capacitance are varied ${\pm}5%$.

• Journal of Korea Technical Association of The Pulp and Paper Industry
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• v.38 no.2 s.115
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• pp.1-8
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• 2006

In this study a process simulation method was used to analyze the accumulation phenomena of anionic starch in the process white water as the closure level of a fine paper making process is increased. A pilot paper machine was used as a model process. Dynamic simulations of the influence of white water usage ratio and uncoated broke addition ratio on the variation of process variable was monitored as a function of time. Results from the dynamic simulations showed that the volume of reservoirs affected the dynamic behavior of the process. The dynamic behavior of flow rate and dissolved starch concentration in process units were different from each other. The speed of the change of dissolved starch concentration in process units was depend on the starting point of the change of dissolved starch concentration, the length of circulation loop, and the volume of reservoirs.

• Journal of the Korea Safety Management & Science
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• v.18 no.4
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• pp.179-183
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• 2016

The purposes of this research are to modelize test system of SM TESTING by ARENA, software, input several items of specimen's testing process, resources of system and transfer loop, etc, give a hypothesis and then, obtain results reducing the efficiency of the whole system finally by overload of specific facilities in the testing system through the simulation so as to obtain several materials such as specimen and testing facility, transfer loop, etc. by simple and various forms without any necessity of numerical modelization. It will add facilities of over load and reduce facilities with low operation rate, so increase the efficiency of the system.

• 제어로봇시스템학회:학술대회논문집
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• 1992.10a
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• pp.194-199
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• 1992

In this paper, each section of an Electrolytic Tinning Line is mathematically modelled with the coupling effect accounted for. Based on the modelling, PI and feedforward controllers are designed for speed control or tension control of each section of the process line. It is shown through simulatios that the tension of the stip is controlled precisely along the entire line and the contituety of the process is insured when using the efficient control of loop towers.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.5
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• pp.949-954
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• 2007

In this work, temperature stable frequency-to-voltage converter is proposed. In FVC circuit input frequency is converted into output voltage signal. A FLL is similar to PLL in the way that it generates an output signal which tracks an input reference signal. A PLL is built on a phase detector, a charge pump, and a low pass filter. However, FLL does not require the use of the phase detector, the charge pump and low pass filter. The FVC is designed by using $0.25{\mu}m$ CMOS process technology. From simulation results, the variation of output voltage is less than ${\pm}2%$ in the temperature range $0^{\circ}C\;to\;75^{\circ}C$ when the input frequency is from 70MHz to 140MHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.5
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• pp.99-105
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• 2014

A reference spur suppressed PLL with two-symmetrical loops without changing the bandwidth which is optimized to suppress phase noise and reduce locking time has been designed. The principle of suppressing a reference signal spur is to stabilize the input voltage of voltage controlled oscillator (VCO). The proposed PLL consists of a phase-frequency detector(PFD) which has two outputs, two charge pumps(CP), two loop filters(LF), a divider and a VCO which has two inputs. Simulation results with $0.18{\mu}m$ CMOS process show that the reference spur is approximately suppressed to 1/2 of the reference spur in a conventional PLL. Even though there is a 5% process variation in the magnitude of R and C, the simulation result shows that the reference spur is still suppressed to 1/2 of the reference spur in a conventional PLL. The power consumption is 6.3mW at the power supply of 1.8V.

• Transactions of the Korean Society of Automotive Engineers
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• v.21 no.1
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• pp.128-136
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• 2013

This study presents the development of Gateway Control Module using SAE J1939 protocol for the commercial vehicles. Presently, the load rate of CAN bus is increased by the single network composition and addition of new ECUs for development of intelligent vehicles. Because the embedded system of the integrated network control function has the errors of the CAN bus caused by the increase of ECU, it is needed for development of commercial vehicles. Also, this study presents the development of smart functions that can diagnosis CAN bus errors, fault diagnosis of ECU and basic function that arbitrates CAN bus between ECUs of commercial vehicle. GCM was designed for 4channel separation about Gateway function as solution of load rate decrease and smart functions. HILS(Hardware in the loop simulation)system that can achieve simulation about CAN Messages of all systems on vehicle was applied to evaluate performance and verification of all functions and performance. The load rate on CAN bus was decreased at using functions what was delivery, block and process of GCM. Through this, it was enabled to organize systematic architecture for gateway.

• Journal of Agricultural Extension & Community Development
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• v.24 no.2
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• pp.99-115
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• 2017

The purpose of this study is to analyze potential adoption rates and reusing patterns of the new rice direct seeding technology. The model constructed and employed in this study is a system dynamics model of farmer adoption and reusing patterns for this new technology over time. The model incorporates a causal loop diagram that explains interactions among rice cultivation subsystems with feedback loops and further attempts to build a causal loop model with stock-flow diagram for computer simulation. As one example of how the model can be used to provide insight to rice farmers, simulations are run over varying levels on the cultivation process of rice. The major finding is to demonstrate the utility of system dynamics simulation methodology in aiding the rice wet direct seeding farmers' decision making.