• Title/Summary/Keyword: process in the loop simulation

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Development of Operation Network System and Processor in the Loop Simulation for Swarm Flight of Small UAVs (소형 무인기들의 군집비행을 위한 운영 네트워크 시스템과 PILS 개발)

  • Kim, Sung-Hwan;Cho, Sang-Ook;Cho, Seong-Beom;Park, Choon-Bae
    • Journal of Institute of Control, Robotics and Systems
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    • v.18 no.5
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    • pp.433-438
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    • 2012
  • In this paper, a operation network system equipped with onboard wireless communication systems and ground-based mission control systems is proposed for swarm flight of small UAVs. This operating system can be divided into two networks, UAV communication network and ground control system. The UAV communication network is intend to exchange the informations of navigation, mission and flight status with minimum time delay. The ground control system consisted of mission control systems and UDP network. Proposed operation network system can make a swarm flight of various UAVs, execute complex missions decentralizing mission to several UAVs and cooperte several missions. Finally, PILS environments are developed based on the total operating system.

Model Based Design and Validation of Vehicle Safety Power Window Control Systems (자동차 Safety Power Window 제어시스템의 모델기반 설계 및 검증)

  • Lee, Do-Hyun;Kim, Byeong-Woo;Choi, Jin-Kwon
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.59 no.12
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    • pp.2298-2305
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    • 2010
  • The paper presents the Model Based Design(MBD) method which design and verify control algorithm for safety power window. Safety power window are required to work together with the anti-pinch function and have to meet FMVSS118 S5 requirements and equivalent ECC requirements. To meet the requirements, this paper presents the establishment of SILS and RCP environments. The design process can reduce time and support more performance-assured design. As a result of study, it met the regulations and achieved reaction force that close to common products.

A low noise PLL with frequency voltage converter and loop filter voltage detector (주파수 전압 변환기와 루프 필터 전압 변환기를 이용한 저잡음 위상고정루프)

  • Choi, Hyek-Hwan
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.14 no.1
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    • pp.37-42
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    • 2021
  • This paper presents a jitter and phase noise characteristic improved phase-locked loop (PLL) with loop filter voltage detector(LFVD) and frequency voltage converter(FVC). Loop filter output voltage variation is determined through a circuit made of resistor and capacitor. The output signal of a small RC time constant circuit is almost the same as to loop filter output voltage. The output signal of a large RC time constant circuit is the average value of loop filter output voltage and becomes a reference voltage to the added LFVD. The LFVD output controls the current magnitude of sub-charge pump. When the loop filter output voltage increases, LFVD decreases the loop filter output voltage. When the loop filter output voltage decreases, LFVD increases the loop filter output voltage. In addition, FVC also improves the phase noise characteristic by reducing the loop filter output voltage variation. The proposed PLL with LFVD and FVC is designed in a 0.18um CMOS process with 1.8V power voltage. Simulation results show 0.854ps jitter and 30㎲ locking time.

Design of an Integer-N Phase.Delay Locked Loop (위상지연을 이용한 Integer-N 방식의 위상.지연고정루프 설계)

  • Choi, Young-Shig;Son, Sang-Woo
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.6
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    • pp.51-56
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    • 2010
  • In this paper, a novel Integer-N phase-delay locked loop(P DLL) architecture has been proposed using a voltage controlled delay line(VCDL). The P DLL can have the LF of one small capacitance instead of the conventional second or third-order LF. The size of chip is $255{\mu}m$ $\times$ $935.5{\mu}m$ including the LF. The proposed P DLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

Cutting Process Modeling of End-Milling in a Closed-Loop Configuration (공구 공작물간의 상대변위를 고려한 엔드밀링의 절삭공정 모델링)

  • 황철현;조동우
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 1995.10a
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    • pp.1059-1062
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    • 1995
  • In cutting system, relative displacement between rool and workpiece is very important. Even though there have been so many works for modeling cutting process of end-milling, most of them have considered only one displacement of either tool or workpiece instead of both. In this paper, the relative displacement between tool and workpiece is considered for modeling cutting process of end-milling using simple experimental modal analysis and cutting force simulation program is developed. In cutting force model, instantaneous uncut chip thickness model is used and Runge-Kutta method is used for the simulation of time varying cutting system.

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Development of Automatic flight Control System for Low Cost Unmanned Aerial Vehicle (저가형 무인 항공기의 자동비행시스템 개발)

  • Yoo, Hyuk;Lee, Jang-Ho;Kim, Jae-Eun;An, Yi-Ki
    • Journal of Institute of Control, Robotics and Systems
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    • v.10 no.2
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    • pp.131-138
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    • 2004
  • Automatic flight control system (AFCS) for a low-cost unmanned aerial vehicle is described in this paper. Development process and block diagram of the AFCS are introduced. The flight control law for longitudinal and lateral channel autopilot is designed using optimization process. In this procedure, the performance index is composed of desired location of closed loop system poles and H$_2$norm of the resultant flight control system. This procedure is applied to the autopilot design of an unmanned target vehicle. Performance of the AFCS is evaluated by processor-in-the-loop simulation test and flight test. These results show that the AFCS has acceptable performance fur low cost UAV.

Initial Frequency Preset Technique for Fast Locking Fractional-N PLL Synthesizers

  • Sohn, Jihoon;Shin, Hyunchol
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.17 no.4
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    • pp.534-542
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    • 2017
  • This paper presents a fast locking technique for a fractional-N PLL frequency synthesizer. The technique directly measures $K_{VCO}$ on a chip, computes the VCO's target tuning voltage for a given target frequency, and directly sets the loop filter voltage to the target voltage before the PLL begins the normal closed-loop locking process. The closed-loop lock time is significantly minimized because the initial frequency of the VCO are put very close to the desired final target value. The proposed technique is realized and designed for a 4.3-5.3 GHz fractional-N synthesizer in 65 nm CMOS and successfully verified through extensive simulations. The lock time is less than $12.8{\mu}s$ over the entire tuning range. Simulation verifications demonstrate that the proposed method is very effective in reducing the synthesizer lock time.

Adaptive Control Design for Missile using Neural Networks Augmentation of Existing Controller (기존제어기와 신경회로망의 혼합제어기법을 이용한 미사일 적응 제어기 설계)

  • Choi, Kwang-Chan;Sung, Jae-Min;Kim, Byoung-Soo
    • Journal of Institute of Control, Robotics and Systems
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    • v.14 no.12
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    • pp.1218-1225
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    • 2008
  • This paper presents the design of a neural network based adaptive control for missile is presented. The application model is Exocet MM40, which is derived from missile DATCOM database. Acceleration of missile by tail Fin control cannot be controllable by DMI (Dynamic Model Inversion) directly because it is non-minimum phase system. So, the inner loop consists of DMI and NN (Neural Network) and the outer loop consists of PI controller. In order to satisfy the performances only with PI controller, it is necessary to do some additional process such as gain tuning and scheduling. In this paper, all flight area would be covered by just one PI gains without tuning and scheduling by applying mixture control technique of conventional controller and NN to the outer loop. Also, the simulation model is designed by considering non-minimum phase system and compared the performances to distinguish the validity of control law with conventional PI controller.

A DYNAMIC SIMULATION OF THE SULFURIC ACID DECOMPOSITION PROCESS IN A SULFUR-IODINE NUCLEAR HYDROGEN PRODUCTION PLANT

  • Shin, Young-Joon;Chang, Ji-Woon;Kim, Ji-Hwan;Park, Byung-Heung;Lee, Ki-Young;Lee, Won-Jae;Chang, Jong-Hwa
    • Nuclear Engineering and Technology
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    • v.41 no.6
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    • pp.831-840
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    • 2009
  • In order to evaluate the start-up behavior and to identify, through abnormal operation occurrences, the transient behaviors of the Sulfur Iodine(SI) process, which is a nuclear hydrogen process that is coupled to a Very High Temperature Gas Cooled Reactor (VHTR) through an Intermediate Heat Exchanger (IHX), a dynamic simulation of the process is necessary. Perturbation of the flow rate or temperature in the inlet streams may result in various transient states. An understanding of the dynamic behavior due to these factors is able to support the conceptual design of the secondary helium loop system associated with a hydrogen production plant. Based on the mass and energy balance sheets of an electrodialysis-embedded SI process equivalent to a 200 $MW_{th}$ VHTR and a considerable thermal pathway between the SI process and the VHTR system, a dynamic simulation of the SI process was carried out for a sulfuric acid decomposition process (Second Section) that is composed of a sulfuric acid vaporizer, a sulfuric acid decomposer, and a sulfur trioxide decomposer. The dynamic behaviors of these integrated reactors according to several anticipated scenarios are evaluated and the dominant and mild factors are observed. As for the results of the simulation, all the reactors in the sulfuric acid decomposition process approach a steady state at the same time. Temperature control of the inlet helium is strictly required rather than the flow rate control of the inlet helium to keep the steady state condition in the Second Section. On the other hand, it was revealed that the changes of the inlet helium operation conditions make a great impact on the performances of $SO_3$ and $H_2SO_4$ decomposers, but no effect on the performance of the $H_2SO_4$ vaporizer.

An Ultra Small Size Phase Locked Loop with a Signal Sensing Circuit (신호감지회로를 가진 극소형 위상고정루프)

  • Park, Kyung-Seok;Choi, Young-Shig
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.14 no.6
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    • pp.479-486
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    • 2021
  • In this paper, an ultra small phase locked loop (PLL) with a single capacitor loop filter has been proposed by adding a signal sensing circuit (SSC). In order to extremely reduce the size of the PLL, the passive element loop filter, which occupies the largest area, is designed with a very small single capacitor (2pF). The proposed PLL is designed to operate stably by the output of the internal negative feedback loop including the SSC acting as a negative feedback to the output of the single capacitor loop filter of the external negative feedback loop. The SSC that detects the PLL output signal change reduces the excess phase shift of the PLL output frequency by adjusting the capacitance charge of the loop filter. Although the proposed structure has a capacitor that is 1/78 smaller than that of the existing structure, the jitter size differs by about 10%. The PLL is designed using a 1.8V 180nm CMOS process and the Spice simulation results show that it works stably.