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http://dx.doi.org/10.17661/jkiiect.2021.14.6.479

An Ultra Small Size Phase Locked Loop with a Signal Sensing Circuit  

Park, Kyung-Seok (Department of Electronic Engineering, Pukyong National University)
Choi, Young-Shig (Department of Electronic Engineering, Pukyong National University)
Publication Information
The Journal of Korea Institute of Information, Electronics, and Communication Technology / v.14, no.6, 2021 , pp. 479-486 More about this Journal
Abstract
In this paper, an ultra small phase locked loop (PLL) with a single capacitor loop filter has been proposed by adding a signal sensing circuit (SSC). In order to extremely reduce the size of the PLL, the passive element loop filter, which occupies the largest area, is designed with a very small single capacitor (2pF). The proposed PLL is designed to operate stably by the output of the internal negative feedback loop including the SSC acting as a negative feedback to the output of the single capacitor loop filter of the external negative feedback loop. The SSC that detects the PLL output signal change reduces the excess phase shift of the PLL output frequency by adjusting the capacitance charge of the loop filter. Although the proposed structure has a capacitor that is 1/78 smaller than that of the existing structure, the jitter size differs by about 10%. The PLL is designed using a 1.8V 180nm CMOS process and the Spice simulation results show that it works stably.
Keywords
Negative Feedback; PLL; Single capacitor loop filter; Signal sensing circuit;
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