• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.2
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• pp.123-128
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• 2020

A low phase noise phase locked loop (PLL) with negative feedback loop including frequency variation sensing circuit (FVSC) has been proposed. The FVSC senses the frequency variation of voltage controlled oscillator output signal and controls the volume of electric charge in loop filter capacitance. As the output frequency of the phase locked loop increases, the FVSC reduces the loop filter capacitor charge. This causes the loop filter output voltage to decrease, resulting in a phase locked loop output frequency decrease. The added negative feedback loop improves the phase noise characteristics of the proposed phase locked loop. The size of capacitance used in FVSC is much smaller than that of loop filter capacitance resulting in no effect in the size of the proposed PLL. The proposed low phase noise PLL with FVSC is designed with a supply voltage of 1.8V in a 0.18㎛ CMOS process. Simulation results show the jitter of 273fs and the locking time of 1.5㎲.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.65-70
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• 2008

A novel fast locking dual-loop integer-N phase locked loop(PLL) with adaptive bandwidth scheme is presented. When the PLL is out-of-lock, bandwidth becomes much wider than 1/10 of channel spacing with the wide bandwidth loop. When the PLL is near in-lock, bandwidth becomes narrower than 1/10 of channel spacing with the narrow bandwidth loop. The proposed PLL is designed based on a $0.35{\mu}m$ CMOS process with a 3.3V supply voltage. Simulation results show the fast look time of $50{\mu}s$ for an 80MHz frequency jump in a 200KHz channel spacing PLL with almost 14 times wider bandwidth than the channel spacing.

• Nuclear Engineering and Technology
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• v.52 no.2
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• pp.429-447
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• 2020

The considered simulation tasks are based on an electrometallurgical process development strategy and associated telemanipulator simulation systems are proposed with various scales of experimental facilities. Fundamentally, target facilities are assumed to be operated only by remote handling systems because the considered process is operated in hazardous environments. Futhermore, the feasibility at various scales should be experimentally verified with gradual increase in throughput. In this regard, bench, engineering, and pilot-scale simulation systems are important early-stage tools for assessing the practical operability of the target process with the material handling systems. Such simulation systems are highly customized for applications and are a precursor to larger pilot and demonstration-scale plants. This paper introduced and classified the developed simulator systems for this approach at various scales using remote handling systems which were assembled inside a virtual target facility, and the manmachine interface was included for a more realistic operation of the simulator. The results obtained for each simulator show the feasibility and requirement for improvement of the systems for the considered test issues with respect to the operation and maintenance of the process.

• Journal of the Korean Institute of Telematics and Electronics
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• v.19 no.3
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• pp.37-45
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• 1982

This paper is a sequel of the Part I paper[1] on the modified digital Costas loop. In this Part II we analyze the performance of the system in the presence of noise. It is shown that, when the input signal is corrupted by additive white Gaussian noise, the noise process in the loop becomes Rician as a result of the tan-1 (.) function of the phase error detector. Steady state probability density functions of phase errors of the first-and second-order loops have been obtained by solving the Chapman-Kolmogorov equation numerically. Also, the mean and variance of phase error in the steady state have been obtained analytically, and are compared with the results obtained by computer simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.73-79
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• 2011

This paper describes a reset-free delay-locked loop (DLL) for a memory controller application, with the aid of a hysteresis coarse lock detector. The coarse lock loop in the proposed DLL adjusts the delay between input and output clock within the pull-in range of the main loop phase detector. In addition, it monitors the main loop's lock status by dividing the input clock and counting its multiphase edges. Moreover, by using hysteresis, it controls the coarse lock range, thus reduces jitter. The proposed DLL neither suffers from harmonic lock and stuck problems nor needs an external reset or start-up signal. In a 0.13-${\mu}m$ CMOS process, post-layout simulation demonstrates that, even with a switching supply noise, the peak-to-peak jitter is less than 30 ps over the operating range of 500-1200 MHz. It occupies 0.04 $mm^2$ and dissipates 16.6 mW at 1.2 GHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12A
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• pp.1990-1999
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• 2001

This paper presents a dynamic simulation loop that gives tracking results of 2-color concentric annular ring (CAR) reticle seeker. Our simulation tool includes the target/flare model and a proportional navigation guidance (PNG) loop. The CAR reticle system performances and the flare effects are analyzed in various scenarios. When a flare is present in the field of view (FOV), the simulation results show that the reticle seeker cannot keep a precise target tracking. In this paper, we propose 2-color counter-countermeasure (CCM) using the least mean square (LMS) method to cope with a presence of IR flare. The proposed method makes a simultaneous process in two infrared (IR) wavelength bands: MWIR add SWIR. The simulation results have shown that our adaptive IRCCM algorithm can achieve an effective cancellation of the flare signal with a relatively high intensity.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.26 no.5
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• pp.71-78
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• 2012

This paper presents a digital control solution to process capacitor current feedback of high performance single-phase UPS for non-linear loads. In all UPS the goal is to maintain the desired output voltage waveform and RMS value over all unknown load conditions and transient response. The proposed UPS uses instantaneous load voltage and filter capacitor current feedback, which is based on the double regulation loop such as the outer voltage control loop and inner current control loop. The proposed DSP-based digital-controlled PWM inverter system has fast dynamic response and low total harmonic distortion (THD) for nonlinear load. The control system was implemented on a 32bit Floating-point DSP controller TMS320C32 and tested on a 5[KVA] IGBT based inverter switching at 11[Khz]. The validity of the proposed scheme is investigated through simulation and experimental results.

• Transactions of the Korean hydrogen and new energy society
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• v.28 no.4
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• pp.401-406
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• 2017

When Liquified Natural Gas (LNG) is vaporized into NG for industrial and household usage, tremendous cold energy was transferred from LNG to seawater during phase-changing process. This heat exchanger loop is not only a waste of huge cold energy, but will cause thermal pollution to the coastal fishery area also when cold water was re-injected into the sea. In this study, an innovation design has been performed to reclaim the cold energy for -35 to $62^{\circ}C$ refrigerated warehouse. Conventionally, this was done by installing mechanical refrigeration systems, necessitating tremendous electrical power to drive temperature. A closed loop LNG heat exchangers in series was designed to replace the mechanical or vapor-compression refrigeration cycle by process simulator. The process simulation software of PRO II with provision has been used to simulate this process for various conditions, what to effect on cold energy and used energy for re-liquefaction and evaporation process. In addition, through analysis the effect of the change of LNG supply pressure on sensible and latent heat, optimum operational conditions was suggested for LNG cold energy warehouse.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.73-81
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• 2012

In this paper, a novel phase locked loop has been proposed using an analog band-selection loop. When the PLL is out-lock, the PLL has a fasting locking characteristic with the analog band-selection loop. When the PLL is near in-lock, the bandwidth becomes narrow with the fine loop. A frequency voltage converter is introduced to improve a stability and a phase noise performance. The proposed PLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• Proceedings of the KOR-KST Conference
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• 2002.02a
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• pp.143-159
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• 2002

The performance of two single-barrier three-phase actuated control systems at diamond interchanges was evaluated for various traffic conditions. To emulate the actuated signal control, hardware-in-the-loop system combined with CORSIM simulation program was used. Two performance measures, average delay and total stops, were used for the evaluation process. Results showed that the two three-phase systems gave similar performance in terms of average delay, but not stops. The delay performance of each phasing system was generally dependent on the traffic pattern and ramp spacing. The total stops decreased as the spacing increased, and it was the most sensitive variable that can differentiate between the two three-phase systems. It was also shown that the hardware-in-the-loop control could provide a good method to overcome the limitations of current simulation technology.