• Journal of Power Electronics
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• v.14 no.2
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• pp.217-225
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• 2014

This paper deals with the optimization of the driving techniques for the ZVT synchronous buck converter proposed in [1]. Two new gate drive circuits are proposed to allow this converter to operate by only one control signal as a 12V voltage regulator module (VRM). Voltage-driven method is applied for the synchronous rectifier. In addition, the control signal drives the main and auxiliary switches by one driving circuit. Both of the circuits are supplied by the input voltage. As a result, no supply voltage is required. This approach decreases both the complexity and cost in converter hardware implementation and is suitable for practical applications. In addition, the proposed SR driving scheme can also be used for many high frequency resonant converters and some high frequency discontinuous current mode PWM circuits. The ZVT synchronous buck converter with new gate drive circuits is analyzed and the presented experimental results confirm the theoretical analysis.

• Journal of Power Electronics
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• v.11 no.6
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• pp.880-889
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• 2011

In this paper, a novel Active Voltage Quality Regulator (AVQR) topology with a thyristor rectifier and an adaptive dclink voltage control strategy are proposed. The proposed AVQR can efficiently mitigate the long duration variations (e.g. undervoltages/overvoltages), voltage imbalances and voltage harmonics. Compared with conventional AVQRs, it can regulate the load voltage very well with a much lower dc-link voltage. This is accomplished by replacing the diode rectifier with a thyristor rectifier. Moreover, its dc-link voltage can vary with the deviations of the supply voltage through the proposed adaptive dc-link voltage control strategy. All of these contribute to its significantly higher efficiency for online operating, which is very important and attractive for many applications. The proposed topology and control strategy are theoretically analyzed in detail. Simulation results are also provided in the paper. Finally, the feasibility and effectiveness of the proposed method are verified by means of experimental results from a 2kVA prototype. Both of the simulation and experimental results show that the proposed AVQR can achieve a much higher efficiency and similar regulation performance when compared with the conventional ones.

• Proceedings of the Korean Society of Propulsion Engineers Conference
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• 2012.05a
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• pp.149-152
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• 2012

This paper describes the study of integrated hydrogen supply system for environment friendly propulsion systems of fuel-cell UAV. Diluted hydrochloric acid was used for direct-decomposing solid-state $NaBH_4$ and generating hydrogen. Self-hydrogen pressurized reactor and pressure regulator was introduced for stable hydrogen supply. Prototype of integrated hydrogen supply systems using the solid-state $NaBH_4$ direct-decomposition was designed for performance evaluation and concept demonstration.

• Journal of IKEEE
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• v.27 no.3
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• pp.333-339
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• 2023

The global market for wearable devices is growing, driving demand for efficient PMICs. Wearable PMICs must be highly energy-efficient despite limited hardware resources. Advancements in process technology enable low-power consumption, but traditional analog LDO regulators face challenges with reduced power supply voltage. In this paper, a novel ADC design with a 3-bit continuous-time flash ADC for the coarse loop and a 5-bit discrete-time SAR ADC for the fine loop is proposed for digital LDO, achieving a 34.78 dB SNR and 5.39 bits ENOB in a 55-nm CMOS technology.

• Proceedings of the KIPE Conference
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• 2010.07a
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• pp.514-515
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• 2010

본 논문은 다중출력 스위칭 모드 전원 공급장치의 경부하 상태에서 2차측의 부하 전압안정을 위하여 일반적으로 사용하는 선형 전압조정기의 제어기 내 부하전류정보를 이용하여, 대기모드를 구현함으로써 시스템의 효율을 향상 시켰다. 제안된 회로의 동작원리를 설명하고 이를 시뮬레이션을 통하여 확인하고 20W급 하드웨어 프로토타입을 이용하여 검증하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.10
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• pp.1804-1809
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• 2006

The aim of this Paper is to describe the implementation of a low-power digital front-End Design (FED) that will act as the core of a stand-alone Power dissipation methodology. The design of digital integrated circuits is a large and diverse area, and we have chosen to focus on low power FED. Designs are made from synthesized logic, and we need to consider the low power digital FED including input clock, buffer, latches, voltage regulator, and capacitance-to-voltage counter which have been integrated onto hish bandwidth communication chips and system. These single- chip micro instruments, implemented in a 0.12um CMOS technology operate with a single 0.9V supply voltage, and can be used to monitor dynamic and static power dissipation, Vesture, acceleration junction temperature (Tj), etc.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.2
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• pp.85-90
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• 2009

This paper presents a single supply PLC SoC ASIC with a built-in analog Front-end circuit. To achieve the low power consumption along with low cost, this PLC SoC employs fully CMOS Analog Front End (AFE) and several LDO regulators (LDOs) to provide the internal power for Logic Core, DAC and Input/output Pad driver. The receiver part of the AFE consists of Pre-amplifier, Gain Amplifier and 1 bit Comparator. The transmitter part of the AFE consists of 10 bit Digital Analog Converter and Line Driver. This SoC is implemented with 0.18 ${\mu}m$ 1 Poly 5 Metal CMOS Process. The single supply voltage is 3.3 V and the internal powers are provided using LDOs. The total power consumption is below 30 mA at stand-by mode to meet the Eco-Design requirement. The die size is 3.2 $\times$ 2.8 $mm^{2}$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.10
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• pp.1835-1839
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• 2008

Power management is a very important issue in portable electronic applications. Portable electronic devices require very efficient power management like LDO to increase the battery life. As the voltage variation of battery power is large in the application of cell phone, camera, laptop, automotive, industry application and so on, battery power is not directly used and LDO is used to supply the power of internal circuit. Besides, LDO can supply DC voltage that is lower than bauer voltage and constant DC voltage that is not related to largely fluctuated battery power. In the study, the power-save mode current and IR-drop characteristics are analyzed from a LDO with on-chip fabricated in 0.18-um CMOS technology.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.534-535
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• 2012

The characteristics of wireless power transfer is achieved at high frequencies in short range magnetic resonant wireless power transfer system. Use PFC pre-regulator for power supply of high frequency inverter. Supplied power to high power factor and high efficiency. Accordingly, the input voltage is 110V-220V. The designed of 175W Class with the output voltage of 385V. As a experiment result, maximum power factor and maximum efficiency measured 99% and 97% respectively. Therefore, in this paper, the design of a inductor which is the most important element in PFC converter for short range magnetic resonance wireless power transfer system was studied. Used an CS330125 core through the designed of 175W class. Examination results power loss was 0.2%.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.6
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• pp.135-140
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• 2021

In this paper is a study on system design to prevent accidents using accelerometers. A switching power FET was configured at the power supply stage, and DC-DC converter, a regulator, and an LDO were designed for the power supply. In order to solve the power problem at once, it was divided into two parts, and a 3-axis accelerometer was designed to extract motion information to safely prevent accidents. Microprocessor enables communication through I2C and UART communication ports, and enables debugging through J-LINK. As a result of measuring the acceleration sensor data, it was confirmed that the power is normally cut off to prevent accidents when motion at an angle of 30° or more is detected.