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Semiconductor Characteristics and Design Methodology in Digital Front-End Design  

Jeong, Taik-Kyeong (Myongji University)
Lee, Jang-Ho (Department of Computer Engineering Hongik University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.10, no.10, 2006 , pp. 1804-1809 More about this Journal
Abstract
The aim of this Paper is to describe the implementation of a low-power digital front-End Design (FED) that will act as the core of a stand-alone Power dissipation methodology. The design of digital integrated circuits is a large and diverse area, and we have chosen to focus on low power FED. Designs are made from synthesized logic, and we need to consider the low power digital FED including input clock, buffer, latches, voltage regulator, and capacitance-to-voltage counter which have been integrated onto hish bandwidth communication chips and system. These single- chip micro instruments, implemented in a 0.12um CMOS technology operate with a single 0.9V supply voltage, and can be used to monitor dynamic and static power dissipation, Vesture, acceleration junction temperature (Tj), etc.
Keywords
Digital Circuit;
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