• 한국연소학회:학술대회논문집
• /
• 2012.11a
• /
• pp.49-51
• /
• 2012

In this paper, the integration issue, such as an air-side integration design between the gas turbine and air separation unit, is described and analyzed by the exergy and energy balance of the combined-cycle power block in an IGCC power plant. The results showed that the net power of the system was almost same, but that of the gas turbine was decreased as the integration degree increased. The highest exergy loss was occurred in the combustor of gas turbine, which was affected by the chemical reaction, heat conduction, mass diffusion, and viscous dissipation.

• Proceedings of the KIEE Conference
• /
• 2005.07d
• /
• pp.3058-3060
• /
• 2005

In this paper, the CMOS four-quadrant analog multipliers for low-voltage low-power applications are presented. The circuit approach is based on the characteristic of the LV (Low-Voltage) composite transistor which is one of the useful analog building blocks. SPICE simulations are carried out to examine the performances of the designed multipliers. Simulation results are obtained by $0.25{\mu}m$ CMOS parameters with 2V power supply. The LV composite transistor can easily be extended to perform a four-quadrant multiplication. The multiplier has a linear input range up to ${\pm}0.5V$ with a linearity error of less than 1%. The measured -3dB bandwidth is 290MHz and the power dissipation is $37{\mu}W$. The proposed multiplier is expected to be suitable for analog signal processing applications such as portable communication equipment, radio receivers, and hand-held movie cameras.

• ETRI Journal
• /
• v.29 no.6
• /
• pp.785-793
• /
• 2007

In this paper, we present an integrated rail-to-rail fully differential operational transconductance amplifier (OTA) working at low-supply voltages (1.5 V) with reduced power consumption and showing high DC gain. An embedded adaptive biasing circuit makes it possible to obtain low stand-by power dissipation (lower than 0.17 mW in the rail-to-rail version), while the high DC gain (over 78 dB) is ensured by positive feedback. The circuit, fabricated in a standard CMOS integrated technology (AMS 0.35 ${\mu}m$), presents a 37 V/${\mu}s$ slew-rate for a capacitive load of 15 pF. Experimental results and high values of two quality factors, or figures of merit, show the validity of the proposed OTA, when compared with other OTA configurations.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.5
• /
• pp.1221-1229
• /
• 1996

This paper proposes a heuristic algorithm for low power implementation of combinational circuits. Selecting an input variable for a given function, the proposed algorithm performs Shannon exansion with respect to the variable to reduce the number of gates in the subcircuit realizing the coffactor function, reducting the power dissipation of the implemented circuit. experimental results for the MCNC benchmarks show that the proposed algorithm is effective by generating the circuits consuming the power 48.9% less on the average, when compared to the previous algorithm based on precomputation logic.

• Journal of Electrical Engineering and information Science
• /
• v.3 no.1
• /
• pp.14-20
• /
• 1998

The resistive shunting for the fine control of a Direct Energy Transfer(DET) systems is fully developed, but the non-resistive shunting using variable size solar array segments is in progress. This paper presents the spacecraft power control through switching of solar array segments, which uses a fully regulated DET power regulation. This method eliminates a dissipative element and removes the associated design limitations which arise from the dissipative elements for radiating cooling in deep space. The switching shunt regulator comprises the switched Solar Array Shunt(SAS) modules that regulate the solar array power. These SAS modules connect/disconnect the solar array segments to/from the bus according to the loading in the main bus without significant variations in the dissipation level. In this paper, twelve segments are used in the shunting. In order to verify the basis of analysis, the computational result of an analytic loop gain is performed.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.3
• /
• pp.313-321
• /
• 2014

A low-power low-cost polar transmitter for EDGE is designed in $0.18{\mu}m$ CMOS. A differential delta-sigma modulator (DSM) tunes a three-terminal voltage-controlled oscillator (VCO) to perform RF phase modulation, where the VCO tuning curve is digitally pre-compensated for high linearity and the carrier frequency is calibrated by a dual-mode low-power frequency-locked loop (FLL). A digital intermediate-frequency (IF) pulse-width5 modulator (PWM) drives a complementary power-switch followed by an LC filter to achieve envelope modulation with high efficiency. The proposed transmitter with 9mW power dissipation relaxes the time alignment between the phase and envelope modulations, and achieves an error vector magnitude (EVM) of 4% and phase noise of -123dBc/Hz at 400kHz offset frequency.

• Proceedings of the IEEK Conference
• /
• 2002.07b
• /
• pp.1288-1291
• /
• 2002

In this paper, we present a design of mpeg-4 video codec chip to reduce the power consumption using frame level clock gating and motion estimation skip scheme. It performs 30 grames/s of codec (encoding and decoding) mode with quarter-common intermediate format(QCIF) at 27MHz. A novel low-power techniques were implemented in architectural level, which is 35% of the power dissipation for a conventional CMOS design. This chip performs MPEG-4 Simple Profile Level 2(Simple@L2) and H.263 base mode. Its contains 388,885 gates, 662k bits memory, and the chip size was 9.7 mm x 9.7 mm which was fabricated using 0.35 micron 3-layers metal CMOS technology.

• Journal of IKEEE
• /
• v.17 no.3
• /
• pp.360-364
• /
• 2013

The maximum breakdown voltage's characteristic within the Super Junction MOSFET structure comes from N-Drift and P-Pillar's charge balance. By developing P-Pillar from Planar MOSFET, it was confirmed that the breakdown voltage is improved through charge balance, and by setting the gate voltage at 10V, the characteristic comparisons of Planar MOSFET and Super Junction MOSFET are shown in picture 6. The results show that it had the same breakdown voltage as Planar MOSFET which increased temperature resistance by 87.4% at $.019{\Omega}cm^2$ which shows that by the temperature resistance increasing, the power module's power dissipation improved.

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.253-256
• /
• 2001

This paper introduces the design of high-speed analog- to-digital converter for high-definition TV, camcorders, portable equipments and implemented in a 0.65${\mu}{\textrm}{m}$ CMOS technology. Key circuits developed for low power and high speed A/D converter are a dynamic comparator that consumes no static power, a source follower buffered op amp that achives wide bandwidth using large input devices. The converter achieves low power dissipation of 40-mW at 3.3-V power supply. Measured performance includes 0.53 LSB of INL and 0.48 LSB of DNL while sampling at 60MHz.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.2
• /
• pp.194-201
• /
• 2015

A frequency modulated ultra-wideband (FM-UWB) transmitter with a high-robust relaxation oscillator for subcarrier generation and a dual-path Ring VCO for RF FM is proposed, featuring low power and low complexity. A prototype 3.65-4.25 GHz FM-UWB transceiver employing the presented transmitter is fabricated in $0.18{\mu}m$ CMOS for short-range wireless data transmission. Experimental results show a bit error rate (BER) of $10^{-6}$ at a data rate of 12.5 kb/s with a communication distance of 60 cm is achieved and the power dissipation of 4.3 mW for the proposed transmitter is observed from a 1.8 V supply.