• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1925_1926
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• 2009

This paper describes a novel power management circuitry for reducing the sleeping mode power dissipation. Based on the proposed power management circuitry, the sensor module can be activated by RF wake-up signal, perform designated process and deactivate itself. There is absolutely no power dissipation at the sleeping mode which takes almost time of the operation. The temperature sensor module using solar cell as energy source has been fabricated and tested. Experimental results show that the sensor module with 3300 ${\mu}$F for storage capacitor can transmits RF temperature data to a receiver at a distance of 20 m every 15 second in a normal indoor light condition and keep the capacitor voltage over 9 V. And the sensor module can operate 100 times with a single charging, that means it is possible for the sensor module to transmit every 5 minute for 8 hours without light or any other power input during the night time.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.663-665
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• 2000

We fabricated resistive superconducting fault current limiters (SFCL) based on YBCO thin films grown on 2-inch diameter saphire substrates Two SFCLs with nearly identical properties were connected in series to investigate the simultaneous quench. There was a slight difference in the rate of voltage increase between two SFCL units when they were operated independently. This difference. however, resulted in significantly unbalanced power dissipation between the units. This imbalance was removed by connecting a shunt resistor to an SFCL in parallel. The appropriate values of the shunt resistances were $80{\Omega}$ at $75 V_{rms}$. $100{\Omega}$ at $100 V_{rms}$ and $110{\Omega}$ at $120 V_{rms}$, respectively. Increased power input at high voltages also reduced the initial imbalance in power dissipation. but with increase in film temperature to higher than 200 K.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.461-464
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• 2009

The conventional electro-mechanical circuit break and relay are widely used in large-sized DC power system. However, recently due to high reliability, remote controllability and small power dissipation of a RSPC (Remote Solid State Power Controller), high-friendly DC power systems have increasingly adopted the RSPC as an essential element. In this paper, we have conducted the modeling of a RSPC circuit and the simulation analysis for $I^2t$ curve, respectively.

• Proceedings of the KIPE Conference
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• 2003.07a
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• pp.10-14
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• 2003

This paper deals with the design of heat dissipation system using the forced air cooling method. It suggests the method of appropriately dividing the whole thermodynamic system into analytical subsystems and also presents the correspondent analytic or experimental equations to subsystems. The experimental results on the designed thermodynamic system for 400kw 1GBT inverter show the validity of the proposed design method in the steady state.

• The Korean Journal of Rheology
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• v.6 no.2
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• pp.129-138
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• 1994

공압출되는 sheet die에서 고분자 물질의 비등온 유동유동을 수치모사하였다. 유변학 적 식으로 power-law model을 사용하였고, 격자생성법을 이용한 유한차분법을 사용하였다. 수치계산을 통해 수축채널에서의 온도 분포를 구해보고 점도가 채널에서의 온도 분포를 구 해 보고 점도가 채널에서의 압력강하 및 신장속도에 미치는 영향을 알아보았다. 압력강하는 외부 유체의 점도 및 heat dissipation의 영향을 크게 받았다. 신장속도는 외부 유체의 점도 가 증가함에 따라 커진 반면 내부 유체의 점도가 증가함에 따라 커진반면, 내부 유체의 점 도증가에 따라 감소하였고, heat dissipation에 의해 증가하였다.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.14 no.6
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• pp.129-135
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• 2015

This paper shows significant methods that improve the lifespan of LED modules as well as efficiently using an aluminum heat-sink for LED module in high power. It proposes a method that raises stability and lifespan to protect LED modules and the power unit when the LED module has been used for a long hours at high temperatures. During the research, we applied a method of pulse-width modulation (PWM) in order to prevent the phenomenon that the entire power of a system is turned off and the lifespan is reduced when the LED nodule reacts to the high temperatures. To protect the LED module and SMPS based on high efficiency, a temperature sensor is attached underneath the circuit board and the sensor measures the temperature of circuit board when the LED module is powered on. The electrical power connected to SMPS is controlled by PWM when the temperature of the LED module reaches a particular temperature.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.10
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• pp.1804-1809
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• 2006

The aim of this Paper is to describe the implementation of a low-power digital front-End Design (FED) that will act as the core of a stand-alone Power dissipation methodology. The design of digital integrated circuits is a large and diverse area, and we have chosen to focus on low power FED. Designs are made from synthesized logic, and we need to consider the low power digital FED including input clock, buffer, latches, voltage regulator, and capacitance-to-voltage counter which have been integrated onto hish bandwidth communication chips and system. These single- chip micro instruments, implemented in a 0.12um CMOS technology operate with a single 0.9V supply voltage, and can be used to monitor dynamic and static power dissipation, Vesture, acceleration junction temperature (Tj), etc.

• The KIPS Transactions:PartA
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• v.17A no.1
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• pp.27-32
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• 2010

Logical Effort is a simple hand-calculated method that measures quick delay estimation. It has the advantage of reducing the design cycle time. However, it has shortcomings in designing a path for minimum area or power under a fixed-delay constraint. In this paper, we propose an equal delay model and, based on this, a method of optimizing power-delay efficiency in a logical path. We simulate three designs of an eight-input AND gate using our technique. Our results show about 40% greater efficiency in power dissipation than those of Logical Effort method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.9-16
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• 2004

The state assignment for a finite state machine greatly affects the delay, area, power dissipation, and testabilities of the sequential circuits. In order to improve the testabilities and power consumption, a new state assignment technique based on m-block partition is introduced in this paper. The algorithm minimizes the dependencies between groups of state variables are minimized and reduces switching activity by grouping the states depending on the state transition probability. In the sequel the length and number of feedback cycles are reduced with minimal switching activity on the state variables. Experiment shows significant improvement in testabilities and Power dissipation for benchmark circuits.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.11
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• pp.1051-1055
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• 2010

Software defined radio(SDR) technology implements wireless communication protocols as software instead of dedicated hardware. SDR enables reconfiguration of wireless communication protocols without expensive hardware modification. However, as the SDR systems are equipped with additional programmable processors, they suffer significant power dissipation. This paper proposes a novel power management technique for SDR systems, called the combined modulation and voltage scaling (CMVS). Numerical analyses were performed to evaluate the effectiveness of CMVS. The results show that CMVS minimizes power dissipation while satisfying the given data transfer rate.