The KIPS Transactions:PartA (정보처리학회논문지A)

Korea Information Processing Society (한국정보처리학회)
권호 표지
DOI QR코드

DOI QR Code

On a Logical Path Design for Optimizing Power-delay under a Fixed-delay Constraint

고정 지연 조건에서 전력-지연 효율성의 최적화를 위한 논리 경로 설계

  • 이승호 (울산대학교 컴퓨터정보통신공학부) ;
  • 장종권 (울산대학교 컴퓨터정보통신공학부)
  • Published : 2010.02.28
Download PDF
⟨ Previous Next ⟩

Abstract

Logical Effort is a simple hand-calculated method that measures quick delay estimation. It has the advantage of reducing the design cycle time. However, it has shortcomings in designing a path for minimum area or power under a fixed-delay constraint. In this paper, we propose an equal delay model and, based on this, a method of optimizing power-delay efficiency in a logical path. We simulate three designs of an eight-input AND gate using our technique. Our results show about 40% greater efficiency in power dissipation than those of Logical Effort method.

Logical Effort의 기법은 회로의 지연 값을 간단한 필산으로 신속하게 측정할 수 있는 기술이다. 이 기법은 설계 공정 시간을 절약하는 장점도 있지만 고정 지연이라는 설계조건에서 회로의 면적이나 전력의 최소화를 도출할 수 있는 논리 경로를 설계하는데 약점도 있다. 이 논문에서는 균형 지연 모형을 제안하고 이 방법을 기반으로 논리경로에서 전력-지연 효율성을 최적화하는 기법을 제안하고자 한다. 본 논문의 기법을 사용하여 8-input AND 게이트의 3가지 서로 다른 설계 회로를 모의 시험한 결과 기존 Logical Effort의 기법보다 약 40%정도 전력 소비의 효율성이 향상되었다.

Keywords

References

  1. Carver Mead and Lynn Conway, "Introduction to VLSI systems", Addison Wesley press, 1979
  2. Ivan E. Sutherland, and Robert F. Sproull, "Logical Effort: Designing for Speed on the Back of an Envelope", IEEE Adv. Research in VLSI, MIT Press, 1991.
  3. Ivan Sutherland, Bob Sproull, and David Harris, "“Logical Effort: Designing Fast CMOS Circuits", Morgan Kaufmann Pub., 1999.
  4. Jo Ebergen, Jonathan Gainsley, and Paul Cunningham, "Transistor Sizing: How to Control the Speed and Energy Consumption of a Circuit", Proceedings International Symposium on Advanced Research in Asynchronous Circuits and Systems, IEEE Computer Society Press, 2004.
  5. B. Lasbouygues, S. Engels, R. Wilson, P. Maurine, N. Azemard, and D. Auvergne, "Logical Effort model extension to propagation delay representation, "IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 9, pp. 1677-1684, September 2006. https://doi.org/10.1109/TCAD.2005.857400
  6. Chun-Hui Wu, Shun-Hua Lin, Herming Chiueh, "Logical Effort model extension with temperature and voltage variation", Thermal Investigation of ICs and Systems, 2008.
  7. Haile Yu, Yuk Hei Chan and Leong, P., "FPGA interconnect design using logical effort" Field Programmable Logic and Applications, 2008.
  8. Seung-ho Lee, Jong-kwon Chang, "An Enhanced Transistor Sizing Technique in a Logical Path Considering Efficient Energy Consumption.",The 3rd International Conference on Ubiquitous Information Technologies & Applications, December 2008.
  9. Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, "Digital Integrated Circuits, A Design Perspective", Second Edition, Prentice Hall, 2003.
  10. Neil H.E. Weste and David Harris, "CMOS VLSI Design: A Circuits and Systems Perspective", Addison Wesley, 3rd edition, 2005.

Cited by

  1. Gate Sizing Of Multiple-paths Circuit vol.2, pp.3, 2013, https://doi.org/10.3745/KTCCS.2013.2.3.103