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http://dx.doi.org/10.3745/KIPSTA.2010.17A.1.027

On a Logical Path Design for Optimizing Power-delay under a Fixed-delay Constraint  

Lee, Seung-Ho (울산대학교 컴퓨터정보통신공학부)
Chang, Jong-Kwon (울산대학교 컴퓨터정보통신공학부)
Publication Information
The KIPS Transactions:PartA / v.17A, no.1, 2010 , pp. 27-32 More about this Journal
Abstract
Logical Effort is a simple hand-calculated method that measures quick delay estimation. It has the advantage of reducing the design cycle time. However, it has shortcomings in designing a path for minimum area or power under a fixed-delay constraint. In this paper, we propose an equal delay model and, based on this, a method of optimizing power-delay efficiency in a logical path. We simulate three designs of an eight-input AND gate using our technique. Our results show about 40% greater efficiency in power dissipation than those of Logical Effort method.
Keywords
Logical Effort; Equal Delay Model; Transistor Sizing; Power Dissipation; Gate Sizing;
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