• ETRI Journal
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• v.31 no.6
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• pp.749-754
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• 2009

The design and performance of an InGaAs/InP transimpedance amplifier and post amplifier for 40 Gb/s receiver applications are presented. We fabricated the 40 Gb/s transimpedance amplifier and post amplifier using InGaAs/InP heterojunction bipolar transistor (HBT) technology. The developed InGaAs/InP HBTs show a cut-off frequency ($f_T$) of 129 GHz and a maximum oscillation frequency ($f_{max}$) of 175 GHz. The developed transimpedance amplifier provides a bandwidth of 33.5 GHz and a gain of 40.1 $dB{\Omega}$. A 40 Gb/s data clean eye with 146 mV amplitude of the transimpedance amplifier module is achieved. The fabricated post amplifier demonstrates a very wide bandwidth of 36 GHz and a gain of 20.2 dB. The post-amplifier module was fabricated using a Teflon PCB substrate and shows a good eye opening and an output voltage swing above 520 mV.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.11
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• pp.1262-1270
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• 2007

In this paper, we propose a new distortion cancellation mechanism for a balanced power amplifier structure using the carrier cancellation loop of a feedforward and post-distortion technique. The proposed cross post-distortion balanced linear amplifier can reduce nonlinear components as much as the conventional feedforward amplifier through the output dynamic range and broad bandwidth. Also the proposed system provides higher efficiency than the feedforward. The capacities of power amplifier and error power amplifier in the proposed system are analyzed and compared with those of feedforward amplifier. Also the operation mechanisms of the three kind loops are explained. The proposed cross post-distortion balanced linear power amplifier is implemented at the IMT-2000($f_0=2.14\;GHz$) band. With the commercial high power amplifiers of total power of 240 W peak envelope power fer base-station application, the adjacent channel leakage ratio measurement with wideband code division multiple access 4FA signal shows 18.6 dB improvement at an average output power of 40 dBm. The efficiency of fabricated amplifier Improves about 2 % than the conventional feedforward amplifier.

• Korean Journal of Optics and Photonics
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• v.5 no.2
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• pp.326-332
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• 1994

Performance of soliton based long-haul optical communication system with in-line optical amplifier repeaters are evaluated numerically. To reduce the optical amplifier noise, the amplifier gain is increased and the post amplifier loss is included. By theoretical calculation with 1480 nm co propagating pump, 7 dB amplifier gain and operating the amplifier 1 dB in compression, the spontaneous emission factor can be reduced from 2.37 to 1.45 by increasing the pump power from 3.71 to 11.53 mW and increasing the post amplifier loss from 0 to 10 dB. Then, power penalty can be reduced from 4.09 to 1.20 dB for 8,000'km transmission and the maximum transmission distance is 14,890 km. ,890 km.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.4
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• pp.283-288
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• 2008

A post-linearization technique for the differrential CMOS LNA is presented. The proposed method uses an additional cross-coupled common-source FET pair to cancel out the third-order intermodulation ($IM_3$) current of the main differential amplifier. This technique is applied to enhance the linearity of CMOS LNA using $0.18-{\mu}m$ technology. The LNA achieved +10.2 dBm IIP3 with 13.7 dB gain and 1.68 dB NF at 2 GHz consuming 11.8 mA from a 1.8-V supply. It shows IIP3 improvement by 6.6 dB over the conventional cascode LNA without the linearizing circuit.

• Journal of electromagnetic engineering and science
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• v.7 no.2
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• pp.91-95
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• 2007

In this paper, a new linearization method has been proposed for a CMOS low noise amplifier(LNA) using the Post IM3 Compensator. The fundamental operating theory of the proposed method is to cancel the IM3 components of the LNA output signal by generating another IM3 components, which are out-phase with respect to that of the LNA, from the Post IM3 Compensator. A single stage common-source LNA has been designed to verify the linearity improvement of the proposed method through $0.13{\mu}m$ RF CMOS process for WiBro system. The designed LNA achieves +7.8 dBm of input-referred 3^{rd}$-order intercept point (IIP3) with 13.2 dB of Power Gain, 1.3 dB of noise figure and 5.7mA @1.5V power consumption. IIP3 is compared with a conventional single stage common-source LNA, and it shows IIP3 is increased by +12.5 dB without degrading other features such as gain and noise figure.

• ETRI Journal
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• v.36 no.2
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• pp.214-223
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• 2014

A fully-integrated penta-band reconfigurable power amplifier (PA) is developed for handset Tx applications. The output structure of the proposed PA is composed of the fixed output matching network, power and frequency reconfigurable networks, and post-PA distribution switches. In this work, a new reconfiguration technique is proposed for a specific band requiring power and frequency reconfiguration simultaneously. The design parameters for the proposed reconfiguration are newly derived and applied to the PA. To reduce the module size, the switches of reconfigurable output networks and post-PA switches are integrated into a single IC using a $0.18{\mu}m$ silicon-on-insulator CMOS process, and a compact size of $5mm{\times}5mm$ is thus achieved. The fabricated W-CDMA PA module shows adjacent channel leakage ratios better than -39 dBc up to the rated linear power and power-added efficiencies of higher than around 38% at the maximum linear output power over all the bands. Efficiency degradation is limited to 2.5% to 3% compared to the single-band reference PA.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.11 s.353
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• pp.175-184
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• 2006

In this paper, we describe a 900MHz CMOS RF transceiver using an ISM band for ZigBee applications. The architecture of the designed rx front-end, which consists of a low noise amplifier, a down-mixer, a programmable gain amplifier and a band pass filter. And the tx front-end, which consists of a band pass filter, a programmable gain amplifier, an up-mixer and a drive amplifier. A low-if topology is adapted for transceiver architecture, and the total current consumption is reduced by using a low power topology. Entire transceiver is verified by means of post-layout simulation and is implemented in 0.18um RF CMOS technology. The fabricated chip demonstrate the measured results of -92dBm minimum rx input level and 0dBm maximum tx output level. Entire power consumption is 32mW(@1.8VDD). Die area is $2.3mm{\times}2.5mm$ including ESD protection diode pads.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.4
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• pp.461-466
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• 1999

A CMOS op amp with rail-to-rail input and output ranges is designed in a one-volt supply. The output stage of the op amp is used in a common source amplifier that operates in sub-threshold region to design a low voltage op amp with rail-to-tail output range. To drive heavy resistor and capacitor loads with rail-to-rail output ranges, a common source amplifier which has a low output resistance is utilized. A bulk-driven differential pair and a bulk-driven folded cascode amplifier are used in the designed op amp to increase input range and achieve 1 V operation. Post layout simulation results show that low frequency gain is about 58 ㏈ and gain bandwidth I MHz. The designed op amp has been fabricated in a 0.8${\mu}{\textrm}{m}$ standard CMOS process. The measured results show that this op amp provides rail-to-rail output range, 56㏈ dc gain with 1 MΩ load and has 0.4 MHz gain-bandwidth with 130 ㎊ and 1 kΩ loads.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.51 no.4
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• pp.167-174
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• 2002

This study describes a fetal heart rate(FHR) estimation algorithm using phonogram. Using a phonogram amplifier, various fetal heart sounds are collected in a university hospital. The FHR estimation algorithms consists of a lowpass filter, decimation, envelop detection, pitch detection, and post-processing. The post-processing is the FHR decision procedure using all informations of fetal heart rates. Using the algorithm and other parameters of fetal heart sound, a fetal monitoring software was developed. This can display the original signals, the FFT spectra, FHR and its trajectory. Even though the fetal phonogram amplifier detects the fetal heart sounds well, the sound quality is not so good as the ultrasonography. In case of very week fetal heart sound, autocorrelation of it showed clear periodicity. But two main peaks in one period is an obstacle in pitch detection and peaks are not so vivid. The proposed FHR estimation algorithm showed very accurate and stable results. Since the developed software displays multiple parameters in real time and has convenient functions, it will be useful for the phonogram-style fetal monitoring device.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.53-60
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• 2005

Recently, sub-micron CMOS technologies have taken the place of III-V materials in a number of areas in integrated circuit designs, in particular even for the applications of gjgabit optical communication applications due to its low cost, high integration level, low power dissipation, and short turn-around time characteristics. In this paper, a four-channel transimpedance amplifier (TIA) array is realized in a standard 0.35mm CMOS technology Each channel includes an optical PIN photodiode and a TIA incorporating the fully differential regulated cascode (RGC) input configuration to achieve effectively enhanced transconductance(gm) and also exploiting the inductive peaking technique to extend the bandwidth. Post-layout simulations show that each TIA demonstrates the mid-band transimpedance gain of 59.3dBW, the -3dB bandwidth of 2.45GHz for 0.5pF photodiode capacitance, and the average noise current spectral density of 18.4pA/sqrt(Hz). The TIA array dissipates 92mw p in total from a single 3.3V supply The four-channel RGC TIA array is suitable for low-power, high-speed optical interconnect applications.