• Transactions on Electrical and Electronic Materials
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• v.1 no.2
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• pp.1-6
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• 2000

This article presents the experiments and considerations possible about gate etching in polysilicon when oxygen gas is added in chamber, We propose the novel study with optical emission spectroscopy in polysilicon etching. It is shown that added oxygen gases play an important role in enhencement of density in chlorine gases as a scavenger of silicon from SiCl$\_$x/. And a small amount of Si-O bonds are deposited and then the deposited thin film protect silicon dioxyde against reaction chlorine with silicon in SiO$_2$. Consequently, we can improve the selectivity of polysilicon the silicon dioxide, which is clearly explained in this model.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.1
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• pp.99-102
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• 2002

Pinholes on the thermally grown oxide, which is called gate oxide, on silicon substrate under polysilicon layer are found and its mechanism is analyzed in this paper. The oxide under a polysilicon layer is broken during the plasma etching process of other polysilicon layer. Both polysilicon layers are separated with 0.8${\mu}{\textrm}{m}$ thick oxide deposited by CVD (Chemical Vapor Deposition). Since broken oxide points are found scattered around an arc occurrence point, it is assumed that an extremely high electric field generated near the arc occurrence point makes the gate oxide broken. 1'he arc occurrence point has been observed on the alignment key and is the mark of low yield. It is found that any arc occurrence can cause chips to fail by breaking the gate oxide, even if are occurrence points are found on scribeline.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.1485-1488
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• 1997

The capacity of memory chip has increased vert quickly and 64MDRAM becomes main product in semiconductor manufacturing lines consists of many sequential processes, including etching process. although it needs direct sensing of wafer state for the accurae detching, it depends on indirect esnsing and sample test because of the complexity of the plasma etching. This equipment receives the inner light of etch chamber through the viewport and convets it to the voltage inetnsity. In this paper, EDP voltage signal has a new role to detect etching failure. First, we gathered data(EPD sigal, etching time and etchrate) and then analyzed the relationships between the signal variatin and the etch rate using two neural network modeling. These methods enable to predict whether ething state is good or not per wafer. For experiments, it is used High Density Inductive coupled Plasma(HDICP) ethcing equipment. Experiments and results proved to be abled to determine the etching state of wafer on-line and analyze the causes by modeling and EPD signal data.

• Journal of the Korean Vacuum Society
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• v.8 no.4A
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• pp.490-495
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• 1999

In 0.18 $\mu \textrm m$ LOGIC device, the etch rate of NMOS polysilicons is different from that of PMOS polysilicons due to the state of polysilicon to manufacture gate line. To control the etch profile, we tested the ratio of $Cl_2$/HBr gas and the total chamber pressure, and also we reduced Back He pressure to get the vertical profile. In the case of manufacturing the gate photoresist line, we used Bottom Anti-Reflective Coating (BARC) to protect refrection of light. As a result we found that $CF_4O_2$ gas is good to etch BARC, because of high selectivity and good photoresist line profile after etching BARC. in the results of the characterization of plasma damage to the antenna effect of gate oxide, NO type thin film(growing gate oxide in 0, ambient followed by an NO anneal) is better than wet type thin film(growing gate oxide in $0_2+H_2$ ambient).

• Journal of Sensor Science and Technology
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• v.23 no.2
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• pp.114-121
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• 2014

We report a polysilicon active area membrane field effect transistor (PSAFET) pressure sensor for low stress deflection of membrane. The PSAFET was produced in conventional FET semiconductor fabrication and backside wet etching. The PSAFET located at the front side measured pressure change using 300 nm thin-nitride membrane when a membrane was slightly strained by the small deflection of membrane shape from backside with any physical force. The PSAFET showed high sensitivity around threshold voltage, because threshold voltage variation was composed of fractional function form in sensitivity equation of current variation. When gate voltage was biased close to threshold voltage, a fractional function form had infinite value at $V_{tn}$, which increased the current variation of sensitivity. Threshold voltage effect was dominant right after the PSAFET was turned on. Narrow transistor channel established by small current flow was choked because electron could barely cross drain-source electrodes. When gate voltage was far from threshold voltage, threshold voltage effect converged to zero in fractional form of threshold voltage variations and drain current change was mostly determined by mobility changes. As the PSAFET fabrication was compatible with a polysilicon FET in CMOS fabrication, it could be adapted in low pressure sensor and bio molecular sensor.

• Journal of the Korean Vacuum Society
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• v.15 no.6
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• pp.630-636
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• 2006

Scale down of semiconductor gate pattern will make progress centrally line width into transistor according to the high integration and high density of flash memory semiconductor. Recently, the many researchers are in the process of developing research for using the ONO(oxide-nitride-oxide) technology for the gate pattern give body to line breadth of less 100 nm. Therefore, etch rate and etch profile of the line width detail of less 100 nm affect important factor in a semiconductor process. In case of increasing of the platen power up to 50 W at the ICP etcher, etch rate and PR selectivity showed good result when the platen power of ICP etcher has 100 W. Also, in case of changing of HBr gas flux at the platen power of 100 W, etch rate was decreasing and PR selectivity is increasing. We founded terms that have etch rate 320 nm/min, PR selectivity 3.5:1 and etch slope have vertical in the case of giving the platen power 100 W and HBr gas 35 sccm at the ICP etcher. Also notch was not formed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.9
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• pp.687-692
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• 2011

Hafnium oxide ($HfO_2$) was very advantageous for substitute material of gate on existing transistor. $HfO_2$ has been widely studied due to high contact with polysilicon and thermal stability and also, it is easily etched by using HF solution. In this study, $HfO_2$ and thermal oxide films were etched by wet etch method using chemical etchant. Etch rate of $HfO_2$ and thermal oxide was linearly increased with increasing concentration of HF and temperature but etch rate of $HfO_2$ was higher than thermal oxide due to $H^+$, $F^-$, and $HF_2^-$ ions at below 0.5% concentration of HF. And also, etch selectivity was improved by adding Hydrazine as additive.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.105-110
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• 2008

We have proposed a new structure of poly-silicon thin film transistor(TFT) which was fabricated the LDD region using doping oxide with graded spacer by etching shape retio. The devices of n-channel poly-si TFT's hydrogenated by $H_2$ and $HT_2$/plasma processes are fabricated for the devices reliability. We have biased the devices under the gate voltage stress conditions of maximum leakage current. The parametric characteristics caused by gate voltage stress conditions in hydrogenated devices are investigated by measuring /analyzing the drain current, leakage current, threshold voltage($V_{th}$), sub-threshold slope(S) and transconductance($G_m$) values. As a analyzed results of characteristics parameters, the degradation characteristics in hydrogenated n-channel polysilicon TFT's are mainly caused by the enhancement of dangling bonds at the poly-Si/$SiO_2$ interface and the poly-Si Brain boundary due to dissolution of Si-H bonds. The structure of novel proposed poly-Si TFT's are the simplity of the fabrication process steps and the decrease of leakage current by reduced lateral electric field near the drain region.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.1 s.38
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• pp.1-5
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• 2006

We prepared 80 nm-thick TiSix on each 70 nm-thick amorphous silicon and polysilicon substrate using an RF sputtering with $TiSi_2$ target. TiSix composite silicide layers were stabilized by rapid thermal annealing(RTA) of $800^{\circ}C$ for 20 seconds. Line width of $0.5{\mu}m$ patterns were embodied by photolithography and dry etching process, then each additional annealing process at $750^{\circ}C\;and\;850^{\circ}C$ for 3 hours was executed. We investigated the change of sheet resistance with a four-point probe, and cross sectional microstructure with a field emission scanning electron microscope(FE-SEM) and transmission electron microscope(TEM), respectively. We observe an abrupt change of resistivity and voids at the silicide surface due to interdiffusion of silicide and composite titanium silicide in the amorphous substrates with additional $850^{\circ}C$ annealing. Our result implies that the electrical resistance of composite titanium silicide may be tunned by employing appropriate substrates and annealing condition.