• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1105-1108
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• 2003

In this paper, we have fabricated the hydrogenated n-channel polysilicon thin film transistor (TFT) with LDD structure and have analyzed the hot carrier degradation characteristics by electrical stress. We have compared the threshold voltage (Vth), sub-threshold slope (S), and trans-conductance (Gm) for devices with LDD (Lightly Doped Drain) structure and non-LDD at same active sizes. We have analyzed the hot carrier effects by the hydrogenation in devices. As a analyzed results, the threshold voltage, sub-threshold slope for n-channel poly-si TFT were increased, trans-conductance was decreased. The effects of hydrogenation in n-channel poly-si TFT with LDD structure were shown the lower variations of characteristics than devices of the non-LDD structure with nomal process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.17-22
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• 2004

We developed a new ANGLED display driving method which used both amplitude and pulse width modulation. For pulse width modulation, we divided a picture frame time into S sub-frames. For amplitude modulation, we used three OLED luminance(or current) levels which were controlled by TFT's gate voltages. By combining these two modulation methods, we obtained 35(=243) grey levels. And we designed a new data electrode driving circuit block with two shift registers without using DAC's. To verify the feasibility, we simulated the key circuit components by HSpice with TFT parameters extracted from current-voltage characteristics of 6${\mu}{\textrm}{m}$ channel length polysilicon TFT's. From the simulation results, we found that 320${\times}$240, dual scan, 243 grey level AMOLED display can be designed with this method.

• Journal of Information Display
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• v.6 no.4
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• pp.11-15
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• 2005

We propose a current mode logic circuit design method for LTPS TFT for enhancing circuit operating speed. Current mode inverter/buffers with passive resistive load had been designed and fabricated. Measurement results indicated that the smaller logic swing of the current mode allowed significantly faster operation than the static CMOS. In order to reduce the chip size, both all pTFT and all nTFT active load current mode inverter/buffer had been designed and analyzed by HSPICE simulation. Even though the active load current mode circuits were inferior to the passive load circuits, it was superior to static CMOS gates.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1250-1252
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• 1993

Enhancement mode n-channel TFT leakage current(off current : $V_G<0$) that is little agreement on the conduction mechanism is major disadvantage of poly-silicon TFT in practical use, characteristic analysis and model ing. In this paper, new modeling of leakage current is proposed. The activation energy of leakage current, which is dependent on gate voltage, and leakage current dependent on poly silicon thickness are plausibly explained with this model. This model indicate that the reduction of leakage current is attributable to a decrease of maximum laterial electric field strength in the drain depletion region and to the density of trap.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.6
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• pp.507-511
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• 2006

We investigated accelerated soft error rate (ASER) in static random access memory (SRAM) cells of thin film transistor (TFT) type. The effects on ASER by cell density, buried nwell structure, operational voltage, and polysilicon-2 layer thickness were examined. The increase in the operational voltage, and the decrease in the density of SRAM cells, respectively, resulted in the decrease of ASER values. The SRAM chips with buried nwell showed lower ASER than those with normal well structure did. The ASER decreased as the test distance from alpha source to the sample increased from $7{\mu}m\;to\;15{\mu}m$. As the polysilicon-2 thickness increased up to $1000\;{\AA}$, the ASER decreased exponentially. In conclusion, the best condition for low soft error rate, which is essential to obtain highly reliable SRAM device, is to apply the buried nwell structure scheme and to fabricate thin film transistors with the thick polysilicon-2 layer

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.2
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• pp.111-116
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• 2001

Poly-Si TFT's(Polysilicon thin filmtransistors) have been actively studied due to their applications in active matrix liquid crystal displays and active pull-up devices of CMOS SRAM's. For such applications, the leakage current has to be in the range of sub-picoampere. However, poly-Si TFT's suffer from anomalous high leakage currents, which is attributed to the emission of the traps present at gain boundaries in the drain junction. The leakage current has been analyzed by the field emission via grain-boundary traps and thermionic field emission over potential barrier located at the grain boundary. We found that the models proposed before are not consistent with the experimental results at far as drain-offset poly-Si TFT's we fabricated concern. In this paper, leakage current of drain-offset poly-Si TFT's with different offset lengths was studied. A conduction model based on the thermionic emission of the tunneling electrons is developed to identify the leakage mechanism. It was found that the effective grain size of the drain-offset region is important factor in the leakage current. A good agreement between experimental and simulated results of the leakage current is obtained.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.43-49
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• 2003

Low-temperature polysilicon (LTPS) technology has continued to mature with the passing of each year since LTPS mass production began. The integration of complex circuits has become possible with advances in microprocessing, leading to the realization of panels with highly advanced functions. At the same time, efforts have been made to meet market demands for lower costs, thereby boosting competitive strength. Today, LTPS-TFT LCDs have become standard equipment for the monitors of digital still cameras, and inroads are being made into the massive cellular phone market. Micro displays such as electronic viewfinders, which were previously only possible with high-temperature polysilicon technology, can now also be made with LTPS, thus expanding the scope of the technology. AMOLED displays using the LTPS-TFT as a back plane are also approaching the stage of industrialization. The hidden potential for the OLED to replace the familiar LCD has prompted Widespread anticipation for this emerging technology. This paper reflects on the history of LTPS technology, then looks forward to its future prospects and suggests a variety of potential fields of application.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.239-242
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• 2008

We have investigated the reliability of short channel ($L=1.5{\mu}m$) p-type ELA poly-Si TFTs under hot carrier stress. Threshold voltage of short channel TFT was significantly more shifted to positive direction than that of long channel TFT under the same stress. This result may be attributed to electron trapping at the interface between poly-Si film and gate oxide layer.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.185-188
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• 2002

In this paper, Amorphous silicon on glass substrate was recrytallized to poly-crystalline silicon by solid phase crystallization(SPC) technology The active region of thin film transistor(TFT) was fabricated by amorphous silicon. The output and transfer characteristics of thin film transistor with lightly doped drain(LDD) structure was measured and analyzed. As a results, analyzed TFT's reliability with LDD's length by various kinds argument such as sub-threshold swing coefficient, mobility and threshold voltages were evaluated. Stress effects in TFT were able to improve to the characteristics of turn-on current and hot carrier effects by LDD's length variations

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1502-1504
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• 1996

The effects of electrical stress in hydrogen passivated and as-fabricated poly-Si TFT's are investigated. It is observed that the charge trapping in the gate dielectric is the dominant degradation mechanism in poly-Si TFT's which has been stressed by the gate bias alone while the creation of defects in the poly-Si film is prevalent in gate and drain bias stressed devices. The degradation due to the gate bias stress is dramatically reduced with hydrogenation time while the degradation due to the gate and drain bias stress is increased a little. From the experimental results, it is considered that hydrogenation suppress the charge trapping at gate dielectrics as well as improve the characteristics of poly-Si TFT's.