• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.31 no.10
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• pp.73-78
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• 2003

MEMS technology in the field of aerospace engineering is more important with light weight and high resolution. Therefore the investigation of thin films properties is issued and the residual stress of thin filrns is one of the important problems to solve. Ion implantation without thermal annealing is applied for the stress gradient relaxation of LPCVD polysilicon films used as the structural part in MEMS. He+ and Ar+ ion implantations reduce the stress gradient of polysilicon films. The property modification of polysilicon films by ion implantation is also investigated. The elastic modulus and hardness of polysilicon films with ion implantation is studied by CSM method which is an advanced nano-indentation method. Ion implantation decreases the elastic modulus and hardness of polysilicon films. However, they are improved with increasing ion dose.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.11
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• pp.29-35
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• 2015

The photo-response characteristics of polysilicon based metal-semiconductor-metal (MSM) photodetector structure, depending on deuterium treatment method, was analyzed by means of the dark-current and the light-current measurements. Al/Ti bilayer was used as a Schottky metal. Our purpose is to incorporate the deuterium atoms into the absorption layer of undoped polysilicon, effectively, for the defect passivation. We have introduced two deuterium treatment methods, a furnace annealing and an ion implantation. In deuterium furnace annealing, deuterium bond was distributed around polysilicon surface where the light current flows. As for the ion implantation, even thought it was a convenient method to locate the deuterium inside the polysilicon film, it creates some damages around polysilicon surface. This deteriorated the photo-response in our photodetector structure.

• Proceedings of the Korean Institute of Building Construction Conference
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• 2014.05a
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• pp.240-241
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• 2014

The environmental pollution problem the globally related to global warming arises. In the construction industry the cement mostly use material, generates the great quantity of CO₂ among the fired process and the global warming is more aggravated. In addition, the polysilicon that is the main raw material used in the solar power generation, produces 1 ton and the industrial by-product of 2 tons is generated. In this way, the arising sludge there is not method recycling and it is all discarded. Therefore, in this research, try to present as the fundamental research material for using the polysilicon sludge as the admixture of the cement in order to reduce the amount of the cement. The based on 'KS L ISO 679' was progressed mortar test. the liquidity, air flow rate, setting time, water absorption ratio, flexural and compression strength was measured. According to, appropriate replacement ratio of the polysilicon sludge tries to analyze.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.6
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• pp.38-48
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• 1993

A recessed n-p Juction diode with the self-aligned sturcture is proposed and fabricated by using the polysilicon as an n$^{+}$ diffusion source. The diode structure can be applicable to the emitter-base formation of high performance bipolar divice and the n$^{+}$ polysilicone mitter has an important effect on the device characteristics. The considered parameters for the polysilicon formation are the deposition condition. As$^{+}$ dose for the doping of the polysilicon and the annealing condition using RTP system. The vertical depth profiles of the fabricated diode are obtained by SIMS and the electrical characteristics are analyzed in terms of the ideality factor of diode (n), contact resistance and reverse leakage current. In addition, n$^{+}$-p junction diodes are formed by using the amorphous silicon (of combination of amorphous and polysiliocn) instead of polysilicon and their characteristics are compared with those of the standard sample. The As$^{+}$ dose for the formation of good junction is about 1~2${\times}10^{16}cm^{2}$ at given RTA conditions (1100.deg. C, 10sec).

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.6
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• pp.1581-1584
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• 2008

In dual-polycide-gate structure with butting contact, net doping concentration of polysilicon was decreased due to overlap between $n^+$ and $p^+$ and lateral dopant diffusion in silicide/polysilicon layers. The generation of parasitic Schottky diode in butting contact region is attributed both to the $CoSi_2$-loss due to $CoSi_2$ agglomeration and to the decrease in net doping concentration of polysilicon layer. Parasitic Schottky diode reduces noise margin of sense amplifier in DDI DRAM, which causes column fail. The column fail could be reduced by physical isolation of $n^+/p^+$ polysilicon junction or suppressing $CoSi_2$ agglomeration by using nitrogen implantation into $p^+$ polysilicon before $CoSi_2$ formation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.2
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• pp.114-119
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• 2000

Etch characteristics of SF6/CI2 electron cyclotron resonance (ECR) plasmas have been investigated. Surface reaction of gas plasma with polysilicon was also analysed using X-ray photoelectron spectroscopy (XPS). At the same time, the relationship between surface reaction and the etched profile of polysilicon was examined using XPS. The etch rate of polysilicon and oxide increases with increasing flow rate of SF6 in the SF6/CI2 gas mixture, and tis selectivity also increase also increase. It was also found that as increasing flow rate of SF6 in the SF6/CI2 gas mixture, the atomic% of chlorine detected at surface region decrease, but F and S contents increase. At the same time, when the mixing ratio of SF6 gas increases, the anisotropy of etched polysilicon is sharply decreased in the 0%~10% range of the SF6 mixing ratio, but is rarely varied in the range over 10%, in spite of the large variations in flow rates. It can be explained that the bonding of S-Si due to SiSx(x$\leq$2) compound formed on the etched surface suppress the formation of Si-Cl and 'or Si-F bonding in the silicon etching.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.1
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• pp.99-102
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• 2002

Pinholes on the thermally grown oxide, which is called gate oxide, on silicon substrate under polysilicon layer are found and its mechanism is analyzed in this paper. The oxide under a polysilicon layer is broken during the plasma etching process of other polysilicon layer. Both polysilicon layers are separated with 0.8${\mu}{\textrm}{m}$ thick oxide deposited by CVD (Chemical Vapor Deposition). Since broken oxide points are found scattered around an arc occurrence point, it is assumed that an extremely high electric field generated near the arc occurrence point makes the gate oxide broken. 1'he arc occurrence point has been observed on the alignment key and is the mark of low yield. It is found that any arc occurrence can cause chips to fail by breaking the gate oxide, even if are occurrence points are found on scribeline.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.907-910
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• 2008

The effect of channel length reduction on the electrical characteristics of self-aligned polysilicon TFTs has been investigated by combining experimental characteristics and 2-D numerical simulations. The role of drain induced barrier lowering and floating body effects has been carefully analized using numerical simulations.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.513-518
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• 2006

An investigation of the transport properties of polysilicon TFTs, using sequential laterally solidified, SLS, material, is presented. This material has a location controlled distribution of grain boundaries, GBs, which makes it particularly useful for the analysis of their influence on the performance of polysilicon TFTs, and to address the issue of the role of spatially localised trapping states. The experimental results were analyzed by using numerical simulations, and the effective medium approximation was compared with a discrete grain model.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.536-538
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• 1987

The recrystallization of polysilicon layer deposited on Si was attemped by means of C02 laser annealing. The polysilicon layer was defined in small island patterns ($50{\mu}m{\times}200{\mu}m$) by means of photolithography prior to the annealings. After the annealing an increase of grain size up to about 50um was obtained.