• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 추계학술대회 논문집 학회본부
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• pp.312-315
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• 1995

The base/gate drive suppression method proposed by Joshi and Bose is that which detects the output current polarity of the leg and, according to the polarity, suppresses the base/gate drive of one of the ore switching devices of the leg. This method has the merit that it does not have the conventional dead time problem, reduces the power loss of the driving circuit and others. But this method has difficulty in implementation. In this paper, a new base/gate drive suppression method by detecting not the output current polarity but the output voltage polarity is proposed. The proposed method is easier to implement than Joshi and Bose's method.

• 한국정보통신학회논문지
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• 제19권12호
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• pp.2892-2898
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• 2015

양극성 이중 독립 게이트 실리콘 나노와이어 전계 효과 트랜지스터를 새롭게 제안한다. 제안한 트랜지스터는 극성 게이트와 제어 게이트를 가지고 있다. 극성게이트의 바이어스에 따라서 N형과 P형 트랜지스터의 동작을 결정할 수 있고 제어 게이트의 전압에 따라 트랜지스터의 전류 특성을 제어할 수 있다. 2차원 소자 시뮬레이터를 이용해서 양극성 전류-전압 특성이 동작하도록 두 개의 게이트들과 소스 및 드레인의 일함수를 조사했다. 극성게이트 4.75 eV, 제어게이트 4.5 eV, 소스 및 드레인 4.8 eV일 때 명확한 양극성 특성을 보였다.

• E2M - 전기 전자와 첨단 소재
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• 제8권5호
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• pp.601-605
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• 1995

This study was concerned, after the oxide films(50 [.angs.]) were grown in a furnace and the MOS capacitor fabricated, with experimental comparison and verification about the Interference Effect of Electronic Waves in the ultra thin oxide/silicon interface. The average error was about 0.8404[%] in n'gate/p-sub and about 0.2991[%] in p$^{+}$gate/p-sub. Therefore, it was predicted that the Interference Effect of Electronic Waves can overcome somewhat according to the gate polarity.

• 한국재료학회지
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• 제24권3호
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• pp.135-139
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• 2014

To obtain the transistor with ambipolar transfer characteristics, IGZO/SiOC thin film transistor was prepared on SiOC with various polarities as a gate insulator. The interface between a channel and insulator showed the Ohmic and Schottky contacts in the bias field of -5V ~ +5V. These contact characteristics depended on the polarities of SiOC gate insulators. The transfer characteristics of TFTs were observed the Ohmic contact on SiOC with polarity, but Schottky contact on SiOC with low polarity. The IGZO/SiOC thin film transistor with a Schottky contact in a short range bias electric field exhibited ambipolar transfer characteristics, but that with Ohmic contact in a short range electric field showed unipolar characteristics by the trapping phenomenon due to the trapped ionized defect formation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 추계학술대회 논문집 학회본부
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• pp.316-320
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• 1995

This paper proposes two base/gate drive suppression methods of NPC inverters. The first is the output current polarity detection type, which can be regarded as an extension of Joshi and Bose's method for ordinary inverters. But this method has difficulties in implementation. The second is the output voltage polarity detection type, which is easier to implement than the former. The base/gate drive suppression methods have the merit that it does not have the dead time problem, reduces the power loss of the driving circuit, and others.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.97-98
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• 2006

High current behaviors of the grounded gate extended drain N-type metal-oxide-semiconductor field effects transistor (GG_EDNMOS) electro-static discharge (ESD) protection devices are analyzed. Simulation based contour analyses reveal that combination of BJT operation and deep electron channeling induced by high electron injection gives rise to the 2-nd on-state. Thus, the deep electron channel formation needs to be prevented in order to realize stable and robust ESD protection performance. Based on our analyses, general methodology to avoid the double snapback and to realize stable ESD protection is to be discussed.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.687-690
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• 2003

Experimental results are presented for gate oxide degradation and its effect on device parameters under negative and positive bias stress conditions using NMOSFET's with 3 nm gate oxide. The degradation mechanisms are highly dependent on stress conditions. For negative gate voltage, both hole- and electron-trapping are found to dominate the reliability of gate oxide. However, with changing gate voltage polarity, the degradation becomes dominated by electron trapping. Statistical parameter variations as well as the "OFF" leakage current depend on those charge trapping. Our results therefore show that Si or O bond breakage by electron can be another origin of the investigated gate oxide degradation.gradation.

• 조명전기설비학회논문지
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• 제18권5호
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• pp.42-47
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• 2004

본 연구는 기존에 제안한 방전 AND gate PDP의 문제점을 개선한 연구결과로서 AND gate를 구성하는 DC 방전의 극성을 반대로 설계하여 인접 주사전극에 대한 cross talk 문제를 개선하였다. 또한 기존의 AND gate의 동작이 공간전하에 의한 방전의 비선형성에 의존한 것과는 달리 본 연구에서 제안한 AND gate는 방전 회로에 따라 인가전압이 변화하는 것을 이용한 NOT 논리를 AND gate에 부가하여 동작이 한층 안정해 졌다. 실험 결과4개의 수평 주사전극에 대해 선택적인 어드레스 방전이 가능하였으며 각각 34V와 70V의 AND 방전 및 Data 방전의 동작마진을 얻을 수가 있었다.

• 대한전자공학회논문지
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• 제26권5호
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• pp.52-59
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• 1989

얇은 산화막의 신뢰성을 정전류 스트레스 방법으로 조사하였다. 실험에 사용된 소자는 산화막 두께가 20~25nm인 다결정실리콘 MOS 커패시터 이었다. VLSI 신뢰성 평가에 필수적인 자동측정 및 통계적 데이타분석을 HP9000 컴퓨터를 이용하여 수행하였다.측정한 TDDB 결과로부터 산화막의 결합밀도, 절연파괴 전하량(Qbd), 수명등을 측정한 결과 스트레스를 가하는 극성에 따라서 다른 특성이 나타났다. 결함밀도는 (-) 게이트 주입의 경우에 62개$cm^2$ 이었다. 절연파괴 전하량은 (+) 게이트 주입의 경우 30C/$cm^2$이었고, (-)게이트 주입의 경우가 1.43$cm^2$/A 이었고, (+)게이트 주입의 경우가 1.25$cm^2$/A이었다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제49권2호
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• pp.73-77
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• 2000

A dual-gate SOI SA-LIGBT (shorted-anode lateral insulated gate bipolar transistor) which eliminates the snapback effectively is proposed and verified by numerical simulation. The elimination of the snapback in I-V characteristics is obtained by initiating the hole injection at low anode voltage by employing a dual gate and a floating electrode in the proposed device. For the proposed device, the snapback phenomenon is completely eliminate, while snapback of conventional SA-LIGBT occurs at anode voltage of 11 V. Also, the drive signals of two gates have same polarity by employing the floating electrode, thereby requiring no additional power supply.