• Journal of the Korean Institute of Telematics and Electronics
• /
• v.15 no.3
• /
• pp.18-23
• /
• 1978

In order to improve the efficiency of Cu2-xS-CdS PN junction type solar cell, a method of reducing the series resiatance is considered. In the fabrication of the thin film of Cu2-xS, what has the largest value of conductivity is fabricated at 250 $^{\circ}C$. The thin film of CdS which has beer fabricated at the temperature 250-30$0^{\circ}C$ of the substrate and 800-85$0^{\circ}C$ of evaporating material has the largest value of conductivity and also fairly good photoelectric characteristics. Therefore, the evaporated thin aim type CdS solar cell has been fabricated at the temperature 25$0^{\circ}C$ of the substrate and 800-85$0^{\circ}C$ of the evaporating material, and its efficiency is measured to he 6%.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.22 no.7
• /
• pp.729-736
• /
• 2011

In this paper, we propose a varactor-diodeless voltage-controlled oscillator operating at X-band, and verify the possibility of applying to a receiver for microwave radar signal detection applications. The proposed VCO is realized by only single RF BJT device as a varactor diode is substitued by a intrinsic collector-base PN-junction of the active device which is used to generate negative resistance. The fabricated VCO meets the specification of the receiver, which has a 11.20~11.75 GHz tuning bandwidth with respect to the tuning voltage, 1.0~7.0 V, output power of 9.0~12.0 dBm and linear frequency tuning performance.

• Proceedings of the KIEE Conference
• /
• 1995.11a
• /
• pp.348-351
• /
• 1995

A modified silicon direct bonding method has been developed alloying an intimate contact between grooved and smooth mirror-polished oxide-free silicon wafers. A regular set of grooves was formed during preparation of heavily doped $p^+$-type grid network by oxide-masking und boron diffusion. Void-free bonded interfaces with filing of the grooves were observed by x-ray diffraction topography, infrared, optical. and scanning electron microscope techniques. The presence of regularly formed grooves in bending plane results in the substantial decrease of dislocation over large areas near the interface. Moreover two strongly misoriented waters could be successfully bonded by new technique. Diodes with bonded a pn-junction yielded a value of the ideality factor n about 1.5 and the uniform distribution of series resistance over the whole area of horded pn-structure. The suitability of the modified technique was confirmed by I - V characteristics of power diodes and reversly switched-on dynistor(RSD) with a working area about $12cm^2$. Both devices demonstrated breakdown voltages close to the calculation values.

• Journal of the Korean Vacuum Society
• /
• v.20 no.3
• /
• pp.189-194
• /
• 2011

Si-cell was prepared with various types owing to the etching times textured by the KOH etching solution. The pn junction for solar cell was prepared on p-type Si wafer by the furnace using the $POCl_3$ and oxygen mixed precursor, and the metalization was done using by the Al back electrode and Ag front electrode. Textured Si surface was etched by the pyramid formation. The efficiency and the fill factor was increased in the Si-cell with a large size of pyramids, because of the series resistances decrease depending on the increasing of the photon absorbance. Increasing of the absorbance occurred the induction of the short current and open voltage, and then the efficiency was increased.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.02a
• /
• pp.133-133
• /
• 2010

3-5족 화합물 반도체를 이용한 집광형 삼중 접합 태양전지는 35% 이상의 광변환 효율로 주목을 받고 있다. 일반적으로 삼중 접합 태양전지는 넓은 영역대의 파장을 흡수하기 위해 밴드갭이 다른 InGaP, GaAs, Ge이 사용된다. 그 중 하부셀은 기계적 강도가 높고 장파장을 흡수할 수 있는 Ge이 사용되는데, p-type Ge 기판위에 III-V 결정막 성장 시 5족 원소가 확산되어 pn접합을 형성하게 된다. 이러한 구조를 가진 Ge 하부셀이 효율적으로 홀-전자 쌍을 형성하기 위해서는 두꺼운 베이스와 얇은 에미터 접합이 필요하다. InGaP의 phosphorus는 낮은 확산계수로 인해 GaAs의 arsenic에 비해 얇은 접합이 형성 가능하며, Ge표면 에칭효과가 더 적다는 장점이 있다. 이를 고려해 우리 연구그룹에서는 metalorganic chemical vapor depostion(MOCVD)을 이용하여 Ge기판위에 성장한 InGaP layer의 특성을 관찰해 보았다. <111>로 $6^{\circ}$ 기울어진 p-type Ge(100) 기판위에 MOCVD를 통해 InGaP layer를 형성하였고, 성장된 layer를 atomic force microscope(AFM)와 high-resolution x-ray diffraction(HRXRD)을 이용하여 표면형상, 조성, 응력상태 등을 각각 관찰하였다. 또한 phosphorus 확산에 의해 형성되는 도핑농도는 electrochemical capacitance-voltage(ECV)을 이용하여 관찰하였다. 성장된 Ge기판위의 InGaP layer의 경우 특징적으로 높이 50 nm, 밑변 길이 $1\;{\mu}m$의 경사진 표면을 관찰할 수 있었으며, 이러한 구조는 TMIn과 TMGa의 비율이 증가 할수록 감소하였다. 따라서 이러한 경사진 형태의 구조는 격자 불일치 때문인 것으로 판단된다. 추가적으로 V/III ratio의 최적화를 통해 1.3 nm의 표면 거칠기를 갖는 InGaP layer를 얻을 수 있었다. ECV를 통해 Ge 하부셀의 pn접합 형성을 관찰한 결과 약 160 nm에서 접합이 형성되는 것을 관찰할 수 있었다. 또한, 같은 성장 조건의 샘플을 1000 초 열처리 후에 접합깊이의 변화를 관찰한 결과 180 nm에서 접합이 관찰되었지만, GaAs의 arsenic에 의한 pn접합은 열처리 후에 그 깊이가 170 nm에서 300 nm로 증가 하였다. 따라서 삼중접합 태양전지의 제작 공정을 고려할 경우 phosphorus에 의한 접합 형성이 Ge 하부셀의 동작 특성에 유리할 것으로 판단된다.

• Journal of the Semiconductor & Display Technology
• /
• v.10 no.4
• /
• pp.61-64
• /
• 2011

In order to grow the crystalline solar cells industry continuously, development of alternate low-cost manufacturing processes is required. Plasma doping system is the technique for introducing dopants into semiconductor wafers in CMOS devices. In photovoltaics, plasma doping system could be an interesting alternative to thermal furnace diffusion processes. In this paper, plasma doping system was applied for phosphorus doping in crystalline solar cells. The Plasma doping was carried out in 1~4 KV bias voltages for four minutes. For removing surface damage and formation of pn junction, annealing steps were carried out in the range of $800{\sim}900^{\circ}C$ with $O_2$ ambient using thermal furnace. The junction depth in about $0.35{\sim}0.6{\mu}m$ range have been achieved and the doping profiles were very similar to emitter by thermal diffusion. So, It could be confirmed that plasma doping technique can be used for emitter formation in crystalline solar cells.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.31 no.6
• /
• pp.367-371
• /
• 2018

1,200 V class junction barrier schottky (JBS) diodes and schottky barrier diodes (SBD) were simultaneously fabricated on the same 4H-SiC wafer. The resulting diodes were characterized at temperatures from room temperature to 473 K and subsequently compared in terms of their respective I-V characteristics. The parameters deduced from the observed I-V measurements, including ideality factor and series resistance, indicate that, as the temperature increases, the threshold voltage decreases whereas the ideality factor and barrier height increase. As JBS diodes have both Schottky and PN junction structures, the proper depletion layer thickness, $R_{on}$, and electron mobility values must be determined in order to produce diodes with an effective barrier height. The comparison results showed that the JBS diodes exhibit a larger effective barrier height compared to the SBDs.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.28 no.6
• /
• pp.371-374
• /
• 2015

This paper suggests a high performance lateral super barrier rectifier (Lateral SBR) device which has the advantages of both Schottky diode and pn junction, that is, low forward voltage and low leakage current, respectively. Advantage of the proposed lateral SBR is that it can be easily implemented and integrated in current BCD platform. As a result of simulation using TCAD, BVdss = 48 V, $V_F=0.38V$ @ $I_F=35mA$, T_j = $150^{\circ}C$ were obtained with very low leakage current characteristic of 3.25 uA.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.34D no.8
• /
• pp.41-51
• /
• 1997

The device simulator (BANDIS) which can analyze efficiently the electrical characteristics of the semiconductor devices under the three dimensional stationary conditions on the IBM PC was developed. Poisson, electon and hole continuity equations are discretized y te galerkin method using a tetrahedron as af finite element. The frontal solver which has exquisite data structures and advanced input/output functions is dused for the matrix solver which needs the highest cost in the three dimensional device simulation. The discretization method of the continuity equations used in BANDIS are compared with that of the scharfetter-gummel method used in the commercial three-dimensional device. To verify an accuracy and the efficiency of the discretization method, the simulation results of the PN junction diode and the BJT from BANDIS are compared with those of the commercial three-dimensiional device simulator such as DAVINCI. The maximum relative error within 2% and the average number of iterations needed for the convergence is decreased by more than 20%. The total simulation time of the BJT with 25542 nodes is decreased to about 60% compared with that of DAVINCI.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1995.05a
• /
• pp.227-229
• /
• 1995

Using thermal oxide SiO$_2$ as a dielectrical isolation layer, SOI Hall sensors without pn junction isolation have been fabricated on Si/SiO$_2$/Si structures. The SOI structure was formed by SDB (Si- wafer direct bonding) technology. The Hall voltage and the sensitivity of Si Hall devices implemented on the SDB SOI structure show good linearity with respect to the appled magnetic flux density and supplied current. The product sensitivity of the SDB SOI Hall device is average 600V/V.T. In the trmperature range of 25 to 300$^{\circ}C$, the shifts of TCO(Temperature Coefficient of the Offset Voltage) and TCS(Temperature Coefficient of the Product Sensitivity) are less than ${\pm}$ 6.7x10$\^$-3/ C and ${\pm}$8.2x10$\^$04/$^{\circ}C$, respectively. These results indicate that the SDB SOI structure has potential for the development of Hall sensors with a high-sensitivity and high-temperature operation.