• Proceedings of the Optical Society of Korea Conference
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• 2004.02a
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• pp.150-151
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• 2004

• The Transactions of the Korea Information Processing Society
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• v.6 no.12
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• pp.3447-3455
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• 1999

Database correctness is guaranteed by standard transaction scheduling schemes like two-phase locking for the context of concurrent execution environment in which short-lived ones are normally mixed with long-lived ones. Traditional syntax-oriented serializability notions are considered to be not enough to handle in particular various types of transaction in terms of duration of execution. To deal with this situation, altruistic locking has attempted to reduce delay effect associated with lock release moment by use of the idea of donation. An improved form of altruism has also been deployed in extended altruistic locking in a way that scope of data to be early released is enlarged to include even data initially not intended to be donated. In this paper, we first of all investigated limitations inherent in both altruistic schemes from the perspective of alleviating starvation occasions for transactions in particular of short-lived nature. The idea of two-way donation locking(2DL) has then been experimented to see the effect of more than single donation in distributed database systems. Simulation experiments shows that 2DL outperforms the conventional two-phase locking in terms of the degree of concurrency and average transaction waiting time under the circumstances that the size of long-transaction is in between 5 and 9.

• 전자공학회논문지 IE
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• v.46 no.1
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• pp.1-6
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• 2009

This paper presents the digital PLL architecture and design for improving the frequency detection range and locking time for wide-band frequency synthesizer applications. In this research, a wide-range digital logic quadricorrelator is used for wide-band and fast frequency detector and sigma-delta modulator with 2-bit up-down counter is adopted for DCO control. The proposed digital PLL reduces the phase noise from quantization effect and is suitable for implementation of wide-band fast-locking as well as low power features, which is in high demand for mobile multimedia applications.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.691-693
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• 2017

A novel structure of fast locking phase locked loop (PLL) with time difference detector and Lock status indicator (LSI) is proposed in this paper. Fast locking time is achieved using LSI. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.

• Korean Journal of Optics and Photonics
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• v.10 no.2
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• pp.146-151
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• 1999

We demonstrated a harmonic mode locking scheme that used regeneratie phase modulation to get a high and stable repetition rate in a figure-of-eight fiber soliton laser. From the detected beat spectra of the laser output, a sinusoidal clock freguency tone of 400 MHz, the 96th harmonics of the fundamental mode locking frequency, was extracted with a high Q filter and was used to drive the phase modulator, resulting in stable output of soliton pulse train synchronized with the modulation signal. Generated soliton pulses had FWHM pulsewidth of 930 fs and 3.1 nm linewidth, yielding pulsewidth-bandwidth product of 0.359 that was close to the transform limit. As the modulation frequency always followed the beat frequency of laser modes, stable harmonic mode locking was achieved without the adjustment of the cavity length, which has been commonly required in actively mode-locked lasers.

• Journal of IKEEE
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• v.27 no.4
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• pp.573-578
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• 2023

This paper introduces a new locking technique applicable to high-performance digital Phase-Locked Loops (DPLL). The study employs additional thermometer codes to reduce quantization errors in LC-based Digital Controlled Oscillators (DCO). Despite not implementing the entire DCO codes in thermometer mode, this method effectively reduces quantization errors through enhanced linearity. In the initial locking phase, binary codes are used, and upon completion of locking, the system transitions to thermometer codes, achieving high frequency linearity and reduced jitter characteristics. This approach significantly reduces the number of switches required and minimizes the oscillator's area, especially in applications requiring low DCO gain (Kdco), compared to the traditional method that uses only thermometer codes. Furthermore, the jitter performance is maintained at a level equivalent to that of the thermometer-only approach. The efficacy of this technique has been validated through modeling and design at the RTL level using SystemVerilog and Verilog HDL.

• The KIPS Transactions:PartD
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• v.8D no.1
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• pp.24-31
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• 2001

In this paper, we present an advanced transaction scheduling protocol to improve the degree of concurrency and satisfy the security requirements for multilevel secure database. We adapted two-phase locking protocol, namely traditional syntax-oriented serializability notions, to multilevel secure database. Altruistic locking, as an advanced protocol, has attempted to reduce delay effect associated with lock release moment by use of the idea of donation. An improved form of altruism has also been deployed for extended altruistic locking OffiLl. This is in a way that scope of data to be early released is enlarged to include even data initially not intended to be donated. We also adapted XAL to multilevel secure database and we first of all investigated limitations inherent in both altruistic schemes from the perspective of alleviating starvation occasions for transactions in particular of short-lived nature for multilevel secure database. Our protocol is based on extended altruistic locking for multilevel secure database (XAL/MLS), but a new method, namely two-way donation locking for multilevel secure database (2DL!/-MLS), is additionally used in order to satisfy security requirements and concurrency. The efficiency of the proposed protocol was verified by experimental results.

• ETRI Journal
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• v.29 no.4
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• pp.463-469
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• 2007

A phase-locked loop (PLL) is described which is operable from 0.4 GHz to 1.2 GHz. The PLL has basically the same architecture as the conventional analog PLL except the locking information is stored as digital code. An analog-to-digital converter is embedded in the PLL, converting the analog loop filter output to digital code. Because the locking information is stored as digital code, the PLL can be turned off during power-down mode while avoiding long wake-up time. The PLL implemented in a 0.18 ${\mu}m$ CMOS process occupies 0.35 $mm^2$ active area. From a 1.8 V supply, it consumes 59 mW and 984 ${\mu}W$ during the normal and power-down modes, respectively. The measured rms jitter of the output clock is 16.8 ps at 1.2 GHz.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3097-3099
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• 2000

In this paper, we design PLL for a low jitter and fast locking time that is used a new simple precharged CMOS phase frequency detector(PFD). The proposed PFD has a simple structure with using only 18 transistors. Futhermore, the PFD has a dead zone 25ps in the phase characteristic which is important in low jitter applications. The phase and frequency error detection range is not limited as the case of other precharge type PFDs. the simulation results base on a third order PLL are presented to verify the lock in process with the proposed PFD. the PLL using the new PED is designed using 0.25${\mu}m$ CMOS technology with 2.5V supply voltage.

• Korean Journal of Optics and Photonics
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• v.1 no.2
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• pp.191-197
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• 1990

An experiment on the phase stability of injection-locked beam is done by using AlGaAs semiconductor lasers. The coherence of two beams from the master and slave lasers is measured by interference between the beams in the Twymann-Green interferometer. The phase change of the output beam of the slave laser as a function of the driving current is measured in the Mach-Zehnder interferometer consisted of the master and slave lasers and a value of 2.5radlmA is obtainccl.