• Proceedings of the KIEE Conference
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• 1990.07a
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• pp.332-335
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• 1990

A digital phase-locked loop speed control system of a self-controlled permanent magnet synchronous mortar fed by a voltage source inverter is presented. This paper discribes the hardware and software design of the system. Variable speed control system for self-controlled permanent magnet synchronous motor is proposed. Simulation results demonstrate the validity of proposed methods. This proposed control technique is implemented by using a microprocessor-based system.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.5
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• pp.794-803
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• 2016

This paper propose a sensorless control system of IPMSM with a adaptive back-EMF estimator and improved instantaneous reactive power compensator. A saliency-based back-EMF is estimated by using the adaptive algorithm. The estimated back-EMF is inputted to the phase locked loop(PLL) and the improved instantaneous reactive power(IRP) compensator for estimating the position/speed of the rotor and compensating the error components between the estimated and the actual position, respectively. The stability of the proposed system is achieved through Popov's hyper stability criteria. The validity of proposed algorithm is verified by the simulations and experiments.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.465-470
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• 2010

The charge pump in a phase-locked loop is a key block in determining reference spurs of the VCO output signal. To reduce reference spurs, the current mismatch in the charge pump must be minimized. This paper presents a dual compensation method to reduce the current mismatch. The proposed charge pump and PLL were realized in a $0.18{\mu}m$ CMOS process. Measured current matching characteristics were achieved with less than 1.4% difference and with the current variation of 3.8% in the pump current over the charge pump output voltage range of 0.35-1.35V at 1.8V. The reference spur of the PLL based on the proposed charge pump was measured to be -71dBc.

• Journal of IKEEE
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• v.19 no.2
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• pp.176-185
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• 2015

The study aims to a design hybrid frequency synthesizer in spectrum analyzer and to propose new techniques designed for evasion of in-band spurious. The study focuses on calculating the exact location of multiple phase locked loop of hybrid frequency synthesizer and spurious of direct digital synthesizer to evade in-band spurious outside of frequency range that the user wants to see and thereby simulating technique to improve input related spurious of spectrum analyzer for algorithm. The proposed technique is designed to calculate spurious evasion algorithm in central processing system when in-band spurious arises, and to move output frequency of DDS(direct digital synthesizer) into the place where no in-band spurious exists thereby improving performance of frequency synthesizer. The study used simulation and result representation to prove the effectiveness of the proposed technique.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.6
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• pp.543-546
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• 2017

This paper presents a simple approach for improving the performance of back-electromotive force (back-EMF)-estimation-based sensorless drives for surface-mounted permanent magnet synchronous motors (SPMSM). Similar to conventional approaches, a hypothetical d-q synchronous reference frame model of SPMSM is employed in the proposed approach to estimate the back-EMFs. This approach also employs a dual phase locked loop structure to compensate for the effect of the dead time and parameter uncertainty of the inverter on the estimated back-EMFs. The proposed algorithm is validated by conducting experiments.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.3
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• pp.270-275
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• 2017

This paper proposes a double-phase-locked-loop (PLL) to improve the performance of position estimation in hall sensor-based permanent magnet synchronous motor control. In hall sensor-based control, a PLL is normally used to estimate the rotor position. The proposed Double-PLL consists of two PLLs, including a reset type integrator. The motor control is more accurate and has better performance than conventional PLL, such as a small estimated position ripple. The validity of the proposed algorithm is verified by simulations and experiments.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.281-282
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• 2014

본 논문은 FPGA 기반의 DSC-PLL(Delayed Signal Cancellation - Phase Locked Loop)을 설계하고, 왜곡된 3상전압 조건에서 위상추종결과를 비교실험 하였다. FPGA 구현 알고리즘은 Matlab/Simulink와 연동된 System Generator를 이용하여 DSC-PLL 모델을 설계하고, Verilog HDL 코드로 변환 하였다. 불평형 및 고조파를 포함한 왜곡된 3상 전압 조건에서 FPGA에 구현된 DSC-PLL과 SRF-PLL (Synchronous Reference Frame - Phase Locked Loop)의 d-q축 고조파 감쇠특성 및 위상추종능력을 실험을 통해 비교하였다. DSC-PLL은 약 5.44ms 이내에 d-q축 고조파 성분을 제거함으로써 정상분 기본파 전압의 위상을 빠르게 추종하는 것을 검증하였다.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.494-495
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• 2014

계통에 분산전원을 연계하여 운용하는 경우 인버터는 일반적으로 계통 전압의 위상 정보를 필요로 한다. 그러나 계통 전압의 불평형 또는 왜곡 조건은 계통 위상각 검출에 영향을 주어 정확성을 감소시킨다. 본 논문에서는 계통전압이 왜곡되거나 불평형 상태에서도 위상각 정보를 정확하고 신속하게 검출하기 위해 고속 푸리에 변환을 이용한 새로운 PLL (Phase-Locked Loop) 기법을 제안한다. 제안된 기법은 샘플링 속도와 변환할 시간 범위를 최적화하여 최소한의 연산으로 계통 전압의 위상을 계산한다. 제안된 기법의 타당성이 시뮬레이션을 통해 입증된다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.5
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• pp.893-899
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• 2008

Behavioral level simulations of LDO voltage regulator and phase locked loop(PLL) are performed with CPPSIM, a behavioral-level simulation tool based on C language. The validity of the simulation tool is examined by modeling analog circuits and simulating the circuits. In addition, the designed PLL adopted digital architecture to possess advantages of digital circuits.

• Journal of Electrical Engineering and Technology
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• v.5 no.4
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• pp.606-613
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• 2010

This paper proposes a novel current-based maximum power point tracking (CMPPT) method for a single-phase photovoltaic power conditioning system (PV PCS) by using a modified incremental conductance method. The CMPPT method simplifies the entire control structure of the power conditioning system and uses an inherent current source characteristic of solar cell arrays. Therefore, it exhibits robust and fast response under a rapidly changing environmental condition. Digital phase locked loop technique using an all-pass filter is also introduced to detect the phase of grid voltage, as well as the peak voltage. Controllers of dc/dc boost converter, dc-link voltage, and dc/ac inverter are designed for coordinated operation. Furthermore, a current control using a pseudo synchronous d-q transformation is employed for grid current control with unity power factor. A 3 kW prototype PV PCS is built, and its experimental results are given to verify the effectiveness of the proposed control schemes.