• The Transactions of the Korean Institute of Electrical Engineers B
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• v.53 no.9
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• pp.562-568
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• 2004

The frequency and phase angle of the utility voltage are important in many industrial systems. In the three-phase system, they can be easily known by using the utility voltage vector. However, in the case of single phase system, there are some difficulties in detecting the information of utility voltage. In conventional system, the zero-crossing detection method is widely used, but could not obtain the information of utility voltage instantaneously. In this paper, the new digital PLL control using virtual two phase detector is proposed with a detailed analysis of single-phase digital PLL control for utility connected systems. The experimental results under various utility conditions are presented and demonstrate an excellent phase tracking capability in the single-phase grid-connected operation.

• Journal of information and communication convergence engineering
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• v.3 no.3
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• pp.142-145
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• 2005

In this paper, a new programmable DLL (delay locked loop) based clock synthesizer is proposed. DLL has several inherent advantages, such as no phase accumulation error, fast locking and easy integration of the loop filter. This paper proposes a new programmable DLL that includes a PFD(phase frequency detector), a LSI(lock status indicator), and a VCDL(voltage controlled delay line) to generate multiple clocks. It can generate clocks from 3 to 9 times of input clock with $2{\mu}s$ locking time. The proposed DLL operating in the frequency range of 300MHZ-900MHz is verified by the HSPICE simulation with a $0.35{\mu}m$ CMOS process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.10
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• pp.1982-1990
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• 1994

We implemented a PLDRO(Phase Locked Dielectric Resonator Oscillator) using the concept of the feedback property of PLL(Phase Locked Loop) for Ku-band(10.95-11.70 GHz). The conventional approaches to a PLDRO design use varactor diode tuning method.. But in theis paper, the PLDRO has the advantage of the frequency sensitivity to changes in the supple voltage of the oscillating device without the frequency-variable part by varactor diode voltage-control. and uses a SPD(Sampling Phase Detector) for phase-comparision. The PLDRO is composed of the DRO phase-locked to the reference signal of UHF band by using a SPD for high frequency stability and can be available for European FSS(Fixed Satellite Service) at 10.00GHz. The PLDRO generates the output power of 8.67 dBm at 10.00 GHz and has a phase noise of -81 dBc/Hz at 10 kHz offset from carrier. The hamonic and spurious characteristics have -42.33 dBc and -65dBc respectively. This PLDRO has much better frequency stability, lower phase noise, and more economical effect for a satellite system than conventional DRO.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.4A
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• pp.440-449
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• 2008

In this paper, we propose a 16-QAM carrier recovery loop which is suitable for the implementation of Inmarsat M4 system receiver. Because the frequency offset of ${\pm}924\;Hz$ on signal bandwidth 33.6 kHz is recommended in Inmarsat M4 system specification, carrier recovery loop having stable operation in the channel environment with large relative frequency offset is required. the carrier recovery loop which adopts only PLL can't be stable in relatively large frequency offset environment. Therefore, we propose a carrier recovery loop which has stable operation in large relative frequency offset environment for Inmarsat M4 system. The proposed carrier recovery loop employed differential filter-based noncoherent UW detector which is robust to frequency offset, CP-AFC for initial frequency offset acquisition using UW signal, and 16-QAM DD-PLL for phase tracking using data signal to overcome large relative frequency offset and achieve stable carrier recovery performance. Simulation results show that the proposed carrier recovery loop has stable operation and satisfactory performance in large relative frequency offset environment for Inmarsat M4 system.

• Proceedings of the KSME Conference
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• 2001.06b
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• pp.176-180
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• 2001

In this paper, we have studies the images have been reconstructed by using combination of images which has been acquired by the variation of operating frequency. When inner images has been reconstructed, inner image has been superposition by surface state effect. In this case, image enhancement the phase object and enhance the contrast of inner image. In the result of the specimen for the round defect with 2mm diameter, for the types of the depth are 1.5mm, 2mm, 2.5mm, and 3mm, it has been show that the shape of defect has better than before this processing and phase contrast grow large twice. And we have constructed the acoustic microscope by using quadrature detector that is able simultaneously to acquired the amplitude and phase of the reflected signal. Father more we have studied the reconstruction method of the amplitude and phase images and the enhancement method of the defect images' contrast.

• Proceedings of the KSME Conference
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• 2008.11a
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• pp.322-326
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• 2008

In this paper, we have studied the images which have been reconstructed by using combination of images acquired by the variation of operating frequency. When inner images have been reconstructed, they have been superposed by the surface state effect. In this case, the images of the phase object can be enhanced by the contrast of inner images. There is a kind of specimen, one is a reference block having 1/4T, 1/2T, 3/4T side drilled holes as main run piping material of the steam generator in nuclear power plants. It has been shown that the two results of defect shapes have better than before in this processing and phase contrast grow about twice. And we have constructed the acoustic microscope by using a quadrature detector that enables to acquire the amplitude and phase of the reflected signal simultaneously. Further more we have studied the reconstruction method of the amplitude and phase images, the enhancement method of the defect images' contrast.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.3
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• pp.1-7
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• 2002

This paper presents a new PLL clock generator that can improve a jitter noise characteristics and acquisition process by designing a multi-PFD(Phase Frequency Detector) and an adaptive charge pump circuit. The conventional PLL has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. An advanced multi-structured PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, in which it shows an excellent functionalities in terms of the jitter noises by designing its circuit with the exact dead zone and duty cycle. Our new designed adaptive charge pump in the loop filter of a PLL can improve an acquisition characteristic by adaptively increasing of current. The Hspice simulation is done to evaluate the performance of the proposed circuit. Simulation result shows that our PLL has under 0.01ns in the dead zone, no influence from the duty cycle of input signals and under 50ns in the acquisition time. This circuit will be able to be used in develops of high-performance microprocessors and digital systems.  

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.9
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• pp.1-12
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• 1998

We have implemented receiver for a 3 Dimensional Phased-Array Radar detecting the azimuth angle, the altitude, the range of a target on real time. This system consists of high frequency module, which protects receiver and controls sensitivity, intermediate frequency module, monopulse detector, IQ phase detector, AGC controller. A two-channel receiver with same function is implemented for increasing accuracy of target altitude data by amplitude comparison monopulse method. The TSS sensitivity of the receiver is -98dBm. The bandwidth of the receiver is 500 MHz. We can control the system gain manually by 100 dB when be AGC off. The gain and phase unbalance of two channels is 5 dB and 30 degree, respectively. The image rejection rate of the IQ detector is 30 dB. We used duroid substrate and package- type device.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.1
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• pp.82-86
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• 2009

This work is design of clock and data recovery circuit using system clock. This circuit is composed by PLL(Phase Locked Loop) to make system clock and data recovery circuit. The data recovery circuit using 1/4-rate phase picking Detector helps to reduce clock frequency. It is advantageous for high speed PLL. It can achieve a low jitter operation. The designed CDR(Clock and data recovery) has been designed in a standard $0.18{\mu}m$ 1P6M CMOS technology and an active area $1{\times}1mm^2$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.4
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• pp.1100-1112
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• 1998

In this paper, a novel method of minimizing the phase error is proposed. A DP-PLL system using this method is implemented and its performacnce is investigated, too. The DP-PLL system detects the phase error between reference clock and locally generated system clock. The phase difference is then reported as a PEV(Phase Error Variation), which is propoced from the delayted n-tap rising dege clock circuit with 5ns resolution in the phase detector. The algorithm is used to track the optimal DAC coefficients, which are adjusted from sample to sample in such a way as to minimize the PEV. The proposed method is found to have remarkable good potential for fast and accurate phase error tracking characteristic. The algorithm shows good performance to supress the low frequency jitter.-ending points, we design new basis functions based on the Legendre polynomial and then transform the error signals with them. When applied to synthetic images such as circles, ellipses and etc., the proposed method provides, in overall, outstanding results in respect to the transform coding gain compared with DCT and DST. And in the case when applied to natural images, the proposed method gives better image quality over DCT and comparable results with DST.