• Title/Summary/Keyword: parasitic elements

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A Study of the Landscape Preference for 'Oreu'm by Analyses of Features & Visual Elements ("오름"의 형태와 시각량 분석을 통한 경관선호성 평가)

  • Kim, Sang-Beom;Sim, Woo-Kyung;Rho, Jae-Hyun
    • Journal of the Korean Institute of Landscape Architecture
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    • v.35 no.1 s.120
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    • pp.48-58
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    • 2007
  • The purpose of this study was not only to clearly examine the features of the scenery and visual elements of Oreum (parasitic cones) but also to investigate primary factors in landscape preferences for these cones. This study further attempted to gain basic information for examining the preservation of Oreum in regards to the influence of scenery on the general public. A Multiple Regression Analysis was used for this study for which the independent variable was the area ratio of the fore-, mid-, and background of the view under the feature element and the structure of the scenery at the Oreum. The dependent variables were the preference value, the number of summits, and the highest altitude of the Oreum. All but the highest inclination were positive variables. The area ratio of the Oreum was found to be the most important variable. The area of sky and the area of the distant scenery were shown to be positive explanation variables, while the area to the fore of the view and the area to the middle of the view were shown as negative explanation variable. In the preference for Oreum scenery, which has a high visibility and is clearly outlined against the skyline, it was found that as the hindrance element of visibility near to a visual point or the area ratio increased, the preference for the Oreum scenery decreased.

Reduction of Barrier Height between Ni-silicide and p+ source/drain for High Performance PMOSFET (고성능 PMOSFET을 위한 Ni-silicide와 p+ source/drain 사이의 barrier height 감소)

  • Kong, Sun-Kyu;Zhang, Ying-Ying;Park, Kee-Young;Li, Shi-Guang;Zhong, Zhun;Jung, Soon-Yen;Yim, Kyoung-Yean;Lee, Ga-Won;Wang, Jin-Suk;Lee, Hi-Deok
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.11a
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    • pp.157-157
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    • 2008
  • As the minimum feature size of semiconductor devices scales down to nano-scale regime, ultra shallow junction is highly necessary to suppress short channel effect. At the same time, Ni-silicide has attracted a lot of attention because silicide can improve device performance by reducing the parasitic resistance of source/drain region. Recently, further improvement of device performance by reducing silicide to source/drain region or tuning the work function of silicide closer to the band edge has been studied extensively. Rare earth elements, such as Er and Yb, and Pd or Pt elements are interesting for n-type and p-type devices, respectively, because work function of those materials is closer to the conduction and valance band, respectively. In this paper, we increased the work function between Ni-silicide and source/drain by using Pd stacked structure (Pd/Ni/TiN) for high performance PMOSFET. We demonstrated that it is possible to control the barrier height of Ni-silicide by adjusting the thickness of Pd layer. Therefore, the Ni-silicide using the Pd stacked structure could be applied for high performance PMOSFET.

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A Bluetooth/WiFi Dual-Mode RF Front-End Module Using LTCC Technology (LTCC 기술을 이용한 Bluetooth/WiFi 이중 모드 무선 전단부 모듈 구현)

  • Ham, Beom-Cheol;Ryu, Jong-In;Kim, Jun-Chul;Kim, Dong-Su;Park, Young-Cheol
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.23 no.8
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    • pp.958-966
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    • 2012
  • This paper presents a compact bluetooth/WiFi dual-mode dual-band RF front-end module(FEM) is realized by low temperature co-fired ceramic(LTCC) technology. The proposed RF front-end module consists of a diplexer, baluns in the LTCC substrate, and an SPDT switch, an SP3T switch on the LTCC substrate. In order to reduce the module size and increase integration level, the proposed diplexer and balun are designed using LC lumped elements. The parasitic elements caused by coupling effect between metal pattern layers and ground plane layer are considered during the design. The fabricated dual-mode RF front-end module has 13 pattern layers including three inner ground layers and it occupies less than $3.0mm{\times}3.7mm{\times}0.66mm$.

Performance Impact Analysis of Resistance Elements in Field-Effect Transistors Utilizing 2D Channel Materials (2차원 채널 물질을 활용한 전계효과 트랜지스터의 저항 요소 분석)

  • TaeYeong Hong;Seul Ki Hong
    • Journal of the Microelectronics and Packaging Society
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    • v.30 no.3
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    • pp.83-87
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    • 2023
  • In the field of electronics and semiconductor technology, innovative semiconductor material research to replace Si is actively ongoing. However, while research on alternative materials is underway, there is a significant lack of studies regarding the relationship between 2D materials used as channels in transistors, especially parasitic resistance, and RF (radio frequency) applications. This study systematically analyzes the impact on electrical performance with a focus on various transistor structures to address this gap. The research results confirm that access resistance and contact resistance act as major factors contributing to the degradation of semiconductor device performance, particularly when highly scaled down. As the demand for high-frequency RF components continues to grow, establishing guidelines for optimizing component structures and elements to achieve desired RF performance is crucial. This study aims to contribute to this goal by providing structural guidelines that can aid in the design and development of next-generation RF transistors using 2D materials as channels.

Optimized Design of T-Shaped Microstrip Antenna with Various Dimensions (T형 마이크로스트립 안테나의 면적 비에 따른 최적 설계)

  • Kim, Jin-Bok;Lee, Joong-Geun
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.47 no.5
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    • pp.53-59
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    • 2010
  • There are various types of antenna fed method; coaxial probe, coupling, parasitic elements, and impedance matching. In this paper, the fed method of the proposed antenna is microstrip line type. The high frequency structure simulator (HFSS) is used to analyze the characteristics of the T-shaped microstrip antenna with various patch dimensions. In comparison with the basic microstrip antenna, this proposed T-shaped microstrip antenna with 40.38 % of patch dimensions has the optimum characteristics of resonant frequency, return loss, and radiation pattern at 2.0 GHz band.

A Design of High-speed Power-off Circuit and Analysis (고속 전원차단 회로 설계 제작 및 측정)

  • Jeong, Sang-Hun;Lee, Nam-Ho;Cho, Seong-Ik
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.63 no.4
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    • pp.490-494
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    • 2014
  • In this paper, a design of high-speed power-off circuit and analysis. The incidence of high-dose transient radiation into the silicon-based semiconductor element induces the photocurrent due to the creation of electron-hole pairs, which causes the upset phenomenon of active elements or triggers the parasitic thyristor in the element, resulting in latch-up. High speed power-off circuit was designed to prevent burn-out of electronic device caused by Latch-up. The proposed high speed power-off circuit was configured with the darlington transistor and photocoupler so that the power was interrupted and recovered without the need for an additional circuit, in order to improve the existing problem of SCR off when using the thyristor. The discharge speed of the high speed power interruption circuit was measured to be 19 ${\mu}s$ with 10 ${\mu}F$ and 500 ${\Omega}$ load, which was 98% shorter than before (12.8 ms).

Design and fabrication of Ka-Band Analog Phase Shifter using GaAs Hyperabrupt Junction Varactor Diodes and Reactance Matching (GaAs Hyperabrupt Junction 바랙터 다이오드와 리액턴스 정합을 이용한 Ka-Band 아날로그 위상변화기의 설계)

  • ;Seong-Ik Cho
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.14 no.5
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    • pp.521-526
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    • 2003
  • This paper describes performance data and design information on a reflection-type analog phase shifter used in Ka-band. Arranging a couple of GaAs hyperabrupt junction varactor diode parallel in a circuit, and applying reactance matching method accordingly, it is possible to 831 a large the phase shift. Design equation is formulated theoretically. Since the assembly process is important in Ka-band, this paper also includes the assembly process that is essential to minimize the generation of parasitic elements during the assembly process. It is obtained variable phase shift 220$^{\circ}$${\pm}$7$^{\circ}$ and insertion loss 5 dB${\pm}$1 dB as a measured result larger than the existing figure in Ka-band.

An incompatible 3D solid element for structural analysis at elevated temperatures

  • Yu, Xinmeng;Zha, Xiaoxiong;Huang, Zhaohui
    • Structural Engineering and Mechanics
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    • v.40 no.3
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    • pp.393-410
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    • 2011
  • The eight-node 3D solid element is one of the most extensively used elements in computational mechanics. This is due to its simple shape and easy of discretization. However, due to the parasitic shear locking, it should not be used to simulate the behaviour of structural members in bending dominant conditions. Previous researches have indicated that the introduction of incompatible mode into the displacement field of the solid element could significantly reduce the shear locking phenomenon. In this study, an incompatible mode eight-node solid element, which considers both geometric and material nonlinearities, is developed for modelling of structural members at elevated temperatures. An algorithm is developed to extend the state determination procedure at ambient temperature to elevated temperatures overcoming initially converged stress locking when the external load is kept constant. Numerical studies show that this incompatible element is superior in terms of convergence, mesh insensitivity and reducing shear locking. It is also showed that the solid element model developed in this paper can be used to model structural behaviour at both ambient and elevated temperatures.

Method for High Frequency Modeling of Transformers Using the S-Parameter (S-Parameter를 이용한 변압기의 고주파 모델링 기법)

  • Jung, Hyeonjong;Yoon, Seok;Kim, Yuseon;Bae, Seok;Lim, Yeongseog
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.29 no.9
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    • pp.677-684
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    • 2018
  • In this paper, we propose a method for high-frequency modeling of transformers using the S-parameter. The open and short circuits of the primary and secondary sides were configured, and the reflection coefficient in each circuit was measured using a vector network analyzer. The equivalent circuit elements were extracted from the measured results to model the high-frequency equivalent circuit, and the validity of the method was verified by comparing the measured S-parameters in a 2-port network with the simulation results.

(GaN MODFET Large Signal modeling using Modified Materka model) (Modified Materka model를 이용한 GaN MODFET 대신호 모델링)

  • 이수웅;범진욱
    • Proceedings of the IEEK Conference
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    • 2001.06b
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    • pp.217-220
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    • 2001
  • CaN(gallium nitride) MODFET(modulation doped field effect transistor) large signal model was studied using Modified Materka-Kacprzak large signal MODFET model. using the Dambrine's method[3, at 45MHz-40㎓, Measured S-parameter and DC characteristics. based on measuring results, small signal parameter extraction was conducted. by the cold FET[4]method, measured parasitic elements were de-embedding. Extracted small signal parameters were modeled using modified Materka model, a sort of fitting function reproduce measuring results. to confirm conducted large signal modeling, modeled GaN MODFET's DC, S-parameter and Power characteristics were compared to measured results, respectively. by results were represented comparatively agreement, this paper showed that modified Materka model was useful in the GaN MODFET large signal modeling.

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