• Parasites, Hosts and Diseases
• /
• v.60 no.5
• /
• pp.309-315
• /
• 2022

Inflammatory bowel disease (IBD) is a chronic and recurrent illness of the gastrointestinal tract. Treatment of IBD traditionally involves the use of aminosalicylic acid and steroids, while these drugs has been associated with untoward effects and refractoriness. The absence of effective treatment regimen against IBD has led to the exploration of new targets. Parasites are promising as an alternative therapy for IBD. Recent studies have highlighted the use of parasite-derived substances, such as excretory secretory products, extracellular vesicles (EVs), and exosomes, for the treatment of IBD. In this report, we examined whether EVs secreted by Giardia lamblia could prevent colitis in a mouse model. G. lamblia EVs (GlEVs) were prepared from in vitro cultures of Giardia trophozoites. Clinical signs, microscopic colon tissue inflammation, and cytokine expression levels were detected to assess the effect of GlEV treatment on dextran sulfate sodium (DSS)-induced experimental murine colitis. The administration of GlEVs prior to DSS challenge reduced the expression levels of pro-inflammatory cytokines, including tumor necrosis factor alpha, interleukin 1 beta, and interferon gamma. Our results indicate that GlEV can exert preventive effects and possess therapeutic properties against DSS-induced colitis.

• Proceedings of the KIEE Conference
• /
• 2001.07c
• /
• pp.1896-1898
• /
• 2001

An offset problem caused by the static parasitic capacitors is analyzed and then some techniques to reduce their effect on the capacitive position sensor are presented. Also new offset compensation technique is proposed that by adjusting the magnitudes of the modulating signals independently, the charge imbalance between electrodes caused by the parasitic capacitors is eliminated without sensor gain variation. Simulation results are given to validate the proposed compensation technique.

• Proceedings of the Korea Society for Industrial Systems Conference
• /
• 2002.06a
• /
• pp.195-199
• /
• 2002

This paper describes the effect of substrate back bias of CMOS Inverter. When the substrate back bias applied in body, the MOS transistor threshold voltage increased and drain saturation current decreased. The back gate reverse bias or substrate bias has been widely utilized and the following advantage has suppressing subthreshold leakage, lowering parasitic junction capacitance, preventing latch up or parasitic bipolar transistor, etc. When the reverse voltage applied substrate, this paper stimulated the propagation delay time CMOS inverter.

• Korean Journal of Microbiology
• /
• v.8 no.4
• /
• pp.173-177
• /
• 1970

In this study the effect of aerosol for the control of the parasitic Aspergilli in the sericultural room was investigated. The results obtained are summarized as follows : 1) The aerosol of PPS-A and PPS-B were quite effective for the control of parasitic Aspergilli in the room of sericulture, while the solution of formalin and chlor kalk, on the other hand, were inconclusive. 2) The activities of the aerosol of PPS-A and PPS-B are more effective when it is applied on the upper part of the room than the lower.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.65 no.5
• /
• pp.785-793
• /
• 2016

This paper analyzes an LCL-type isolated dc-dc converter operating for constant output voltage in the continuous conduction mode(CCM) with resistances of parasitic losses-static drain-source on resistance of power switch, ESR of resonant network(L-C-L)-using a high loaded quality factor Q assumptions and fourier series techniques. Simple analytical expressions for performance characteristics are derived under steady-state conditions for designing and understanding the behavior of the proposed converter. The voltage-driven rectifier is analyzed, taking into account the diode threshold voltage and the diode forward resistance. Experimental results measured for a proposed converter at low input voltage and various load resistances show agreement to the theoretical performance predicted by the analysis within maximum 4% error. Especially in the case of low output voltages and large loads, It is been observed that introduction of both rectifier and the parasitic components of converter had considerable effect on the performance.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1998.11a
• /
• pp.13-16
• /
• 1998

An anomalous current characteristics which show the superposition of a low current level and high current level at the subthreshold region when SONOSFETs are in memory states were investigated. We have assumed this phenomena were resulted from the effect of parasitic transistors by LOCOS isolation and were modeled to a parallel equivalent circuit of one memory transistor and two parasitic transistors. Theoretical curves are well fitted in measured log I$_{D}$-V$_{G}$ curves independent of channel width of memory devices. The difference between low current level and high current level is apparently decreased with decrease of channel width of devices because parasitic devices dominantly contribute to the current conduction with decrease of channel width of memory devices. As a result, we concluded that the LOCOS isolation has to selectively adopt in the design of process for charge-trap type NVSM.VSM.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.2
• /
• pp.148-162
• /
• 1996

Bonding wires for high frequency device packaging have dominant parasitic inductances which limit the performance of semiconductor lasers. In this paper, the inductance sof bonding wires are claculated by the method of moments with incorporation of ohmic loss, and the wideband modulation characteristics are analyzed for ddifferent wire lengths and structures. We observed the modulation bandwidth for 1mm-length bonding wire lengths and structures. We observed the modulation bandwidth for 1mm-length bonding wire is 7 GHz wider than that for 2mm-length bonding wire. We also observed th estatic inductance calculation results in dispersive deviation of the parasitic inductance and the modulation characteristics from the wideband moment methods calculations. The angled bonding wire has much less parasitic inductance and improves the modulation bandwidth more than 6 GHz. This calculation resutls an be widely used for designing and packaging of high-speed semiconductor device.

• Transactions on Electrical and Electronic Materials
• /
• v.4 no.2
• /
• pp.15-19
• /
• 2003

In this paper, the new dual trench gate Emitter Switched Thyristor (DTG-EST) is proposed for improving snap-back effect which leads to a lot of serious problems of device applications. Also the parasitic thyristor that is inherent in the conventional EST is completely eliminated in this structure, allowing higher maximum controllable current densities for ESTs. The conventional EST exhibits snap-back with the anode voltage and current density 2.73V and 35A/$\textrm{cm}^2$, respectively. But the proposed DTG-EST exhibits snap-back with the anode voltage and current density 0.96V and 100A/$\textrm{cm}^2$, respectively.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.67 no.4
• /
• pp.538-542
• /
• 2018

In order to generate a clock source with low cost and high performance in system on chip(SoC), a relaxation oscillator with stable output characteristics according to PVT(process, voltage and temperature) fluctuation require a low area and a low power. In this paper, we propose a solution to reduce the current loss caused by parasitic components in the conventional relaxation oscillator. Since the slew rate of the bias current and the capacitor are adjusted to be the same through the proposed solution, a relaxation oscillator with low area characteristics is designed for the same clock source frequency implementation. The proposed circuit is designed using the TSMC CMOS 0.18um process. The Simulation results show that the relaxation oscillator using the proposed solution can prevent the current loss of about $279{\mu}A$ and reduce the total chip area by 20.8% compared with the conventional oscillator in the clock source frequency of 96 MHz.

• ETRI Journal
• /
• v.38 no.1
• /
• pp.133-140
• /
• 2016

This paper presents a method of parasitic inductance reduction for high-speed switching and high-efficiency operation of a cascode structure with a low-voltage enhancement-mode silicon (Si) metal-oxide-semiconductor field-effect transistor (MOSFET) and a high-voltage depletion-mode gallium nitride (GaN) fielde-ffect transistor (FET). The method is proposed to add a bonding wire interconnected between the source electrode of the Si MOSFET and the gate electrode of the GaN FET in a conventional cascode structure package to reduce the most critical inductance, which provides the major switching loss for a high switching speed and high efficiency. From the measured results of the proposed and conventional GaN cascode FETs, the rising and falling times of the proposed GaN cascode FET were up to 3.4% and 8.0% faster than those of the conventional GaN cascode FET, respectively, under measurement conditions of 30 V and 5 A. During the rising and falling times, the energy losses of the proposed GaN cascode FET were up to 0.3% and 6.7% lower than those of the conventional GaN cascode FET, respectively.