• 한국광학회:학술대회논문집
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• 한국광학회 2003년도 제14회 정기총회 및 03년 동계학술발표회
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• pp.148-149
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• 2003

The parasitic effects due to the current blocking layer limit the bandwidth of the semiconductor laser diode. Thus, the parasitic response of various blocking layers was analyzed. The inin type was the best choice for the leakage current reduction and the bandwidth expansion.

• 한국산업정보학회논문지
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• 제21권1호
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• pp.1-6
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• 2016

본 논문에서는 기생 트랜지스터를 억제하여 대기 전류를 낮춰 기동전류를 개선한 수직 PNP 트랜지스터의 특성을 소개한다. 기생 효과를 억제하기 위해, 회로 변경 없이 "DN+ 링크"를 사용하여 기생 PNP 트랜지스터를 억제 시킨 수직 PNP 트랜지스터를 설계하였으며, 표준 IC 프로세서를 이용한 LDO 레귤레이터를 제작했다. 제작된 기생 PNP 트랜지스터의 hFE 가 기존의 18에서 0.9로 감소하였다. 개선된 "DN+ 링크" 구조 수직 PNP 트랜지스터로 제작된 LDO 레귤레이터의 기동 전류는 기존의 기동 전류 90mA에서 32mA 로 감소되었다. 이로 인해 대기상태에서 저 소비전력을 구현한 LDO 레귤레이터를 개발하였다.

• 한국광학회:학술대회논문집
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• 한국광학회 2007년도 하계학술발표회 논문집
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• pp.289-290
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• 2007

We have theoretically derived a electrical model and extracted a parasitic parameters of leakage current in InGaN/GaN light emitting diodes (LEDs). The parasitic parameters of our LED are $R_p=10^{10}{\Omega}$, $I_{0,2}=10^{-17}A$ and $n_2=3.6$, which provide information of leakage current.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 추계학술대회 논문집
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• pp.13-16
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• 1998

An anomalous current characteristics which show the superposition of a low current level and high current level at the subthreshold region when SONOSFETs are in memory states were investigated. We have assumed this phenomena were resulted from the effect of parasitic transistors by LOCOS isolation and were modeled to a parallel equivalent circuit of one memory transistor and two parasitic transistors. Theoretical curves are well fitted in measured log I$_{D}$-V$_{G}$ curves independent of channel width of memory devices. The difference between low current level and high current level is apparently decreased with decrease of channel width of devices because parasitic devices dominantly contribute to the current conduction with decrease of channel width of memory devices. As a result, we concluded that the LOCOS isolation has to selectively adopt in the design of process for charge-trap type NVSM.VSM.

• Journal of Power Electronics
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• 제18권3호
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• pp.892-901
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• 2018

SiC MOSFETs have been used to improve system efficiency in high frequency converters due to their extremely high switching speed. However, this can result in undesirable parasitic oscillations in practical systems. In this paper, models of the key components are introduced first. Then, theoretical formulas are derived to calculate the switching oscillation frequencies after full turn-on and turn-off in clamped inductive circuits. Analysis indicates that the turn-on oscillation frequency depends on the power loop parasitic inductance and parasitic capacitances of the freewheeling diode and load inductor. On the other hand, the turn-off oscillation frequency is found to be determined by the output parasitic capacitance of the SiC MOSFET and power loop parasitic inductance. Moreover, the shifting regularity of the turn-off maximum peak voltage with a varying switching speed is investigated on the basis of time domain simulation. The distortion of the turn-on current is theoretically analyzed. Finally, experimental results verifying the above calculations and analyses are presented.

• 전력전자학회논문지
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• 제25권3호
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• pp.195-203
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• 2020

This paper presents a parasitic inductance reduction design method for the stable driving of GaN HEMT. To reduce the parasitic inductance, we propose a vertical lattice loop structure with multiple loops that is not affected by the GaN HEMT package. The proposed vertical lattice loop structure selects the reference loop and designs the same loop as the reference loop by layering. The design reverses the current direction of adjacent current paths, increasing magnetic flux cancellation to reduce parasitic inductance. In this study, we validate the effectiveness of the parasitic inductance reduction method of the proposed vertical lattice loop structure.

• Tribology and Lubricants
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• 제26권5호
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• pp.277-282
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• 2010

The purpose of this paper is to study and analysis the failure examples for parasitic current leakage produced in starting system on gasoline engine. It verified the discharge of battery by electric leakage because of internal wiring damage problem for CD auto changer installed in car. Also, it verified the no-stating phenomenon because of deposit forming by chemical reaction of battery fluid between battery post and cable fixing parts. It verified the damage for brush holder and commutator mixing by internal short phenomenon because of brush carbon a particle and engine oil that was flowed into internal of starting motor. It verified the working phenomenon of audio by a point of contact even if the driver turn to "LOCK" position the key.

• 전자공학회논문지D
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• 제34D권6호
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• pp.20-32
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• 1997

An optimum parasitic inductance is observed for maximizing the modulation bandwidth of the multiple quantum well (MQW) electro-absorption optical modulator. For 1.1 pF device cpaacitance of the current MQW optical modulator, the optimum parasitic inductances for maximum bandwidth are calculated for different terminating resistors. In ase of 50.ohm. terminating resistor, the 3-dB modulation bandwidth can be increased 45% wider by using the optimum parasitic inductance than nothing parasitic inductance. This calculated optimum inductance can be practically implemented, since the parasitic inductance of bondwires can be accurately analyzed using the method of moments (MoM) and controlled by changing the length and shpae of bondwires.

• 한국광학회지
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• 제14권4호
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• pp.423-428
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• 2003

직접 변조형 반도체 레이저 다이오드에서 전류차단층의 구조들이 누설전류 및 대역폭에 미치는 영향을 조사하였다. 전류차단층을 통한 누설전류는 전류-전압미분특성 곡선을 통하여, 전류차단층의 기생성분들이 대역폭에 미치는 영향은 차감법(Subtraction method)을 사용하여 분석하였다. 실험결과로부터 정적 및 동적특성에 동시에 우수한 특성을 보이는 전류차단층 구조로서‘inin’형 차단구조가 매우 효과적임을 밝혔다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.208-211
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• 1999

Abstract - Electrical characteristics or asymmetric n-MOSFET's with different source and drain geometry are experimently investigated using test structures having various gate width. Saturation drain current and resistance in linear region are estimated by a simple schematic model, which consists of conventional device having parasitic resistor. A comparison of experimental results of symmetric and asymmetric devices gives the parasitic resistance caused by abnormal device structure. The suggested model shows good agreement with the measured drain current for both forward- and reverse-modes.