1 |
J. D. van Wyk and F. C. Lee, "On a future for power electronics." IEEE J. Emerg. Sel. Topics Power Electron., Vol. 1, No. 2, pp. 59-72, Jun. 2013.
DOI
|
2 |
J. L. Hudgins, “Power electronics devices in the future,” IEEE J. Emerg. Sel. Topics Power Electron., Vol. 1, No. 1, pp. 11-17, Mar. 2013.
DOI
|
3 |
J. Millan, P. Godignon, X. perpina, A. Perez-Tomas, and J. Rebollo, “A survey of wide bandgap power semiconductor devices,” IEEE Trans. Power Electron., Vol. 29, No. 5, pp. 2155-2163, May 2014.
DOI
|
4 |
Efficient Power Conversion Corporation, "EPC2015," [Online]. Available: https://epc-co.com.
|
5 |
J. Wang, H. S. Chung, and R. T. Li, “Characterization and experimental assessment of the effects of parasitic elements on the MOSFET switching performance,” IEEE Trans. Power Electron., Vol. 28, No. 1, pp. 573-590, Jan. 2013
DOI
|
6 |
Y. Xiao, H. Shah, T. P. Chow, and R. J. Gutmann, "Analytical modeling and experimental evaluation of interconnect parasitic inductance on MOSFET switching characteristics," in Proc. 19th Annu. IEEE Appl. Power Electron. Conf. Expo., pp. 516-521, Feb. 2004.
|
7 |
Y. Gui and R. Burgos, "Desaturation detection for paralleled GaN E-HEMT phase leg," in Conference Record of the 2018 IEEE ECCE, Sep. 2018.
|
8 |
GaN Systems, "GN001 application guide," [Online]. Available: https://gansystems.com.
|
9 |
G. Skibinski and D. M. Divan, "Design methodology & modeling of low inductance planar bus structure," in Proc. EPE'98 Conf., pp. 98-105, Sep. 1993.
|
10 |
M. C. Caponet, F. Profumo, R. W. D. Doncker, and A. Tenconi, "Low stray inductance bus bar design and construction for good EMC performance in power electronic circuits," IEEE Trans. Power Electron., Vol. 17, No. 2, pp 225-231, Mar. 2002.
DOI
|
11 |
B. J. Baliga, Power semiconductor devices, PWS Publishing Company, Boston, MA, p. 373, 1996.
|
12 |
K. Wang, L. Wang, X. Wang, X. Zeng, W. Chen, and H. Li, “A multiloop method for minimization of parasitic inductance in GaN based high-frequency DC-DC converter,” IEEE Trans. Power Electron., Vol. 32, No. 6, pp. 4728-4740, Jun. 2017.
DOI
|
13 |
T. Hashimoto, T. Kawashima, T. Uno, N. Akiyama, N. Matsuura, and H. Akagi, “A system-in-package (SiP) with mounted input capacitors for reduced parasitic inductances in a voltage regulator,” IEEE Trans. Power Electron., Vol. 25, No. 3, pp. 731-740, Mar. 2010.
DOI
|
14 |
Texas Instruments, "Ringing reduction techniques for NexFET high performance MOSFETs," Texas Instrument, Dallas, TX, USA, Application Rep. SLPA010, Nov. 2011.
|
15 |
D. Reusch and J. Strydom, “Understanding the effect of PCB layout on circuit performance in a high-frequency gallium-nitride-based point of load converter,” IEEE Trans. Power Electron., Vol. 29, No. 4, pp. 2008-2015, Apr. 2014.
DOI
|
16 |
R. P. Clayton, The concept of loop inductance, Wiley-IEEE Press, 2010.
|