• Proceedings of the Optical Society of Korea Conference
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• 2003.02a
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• pp.148-149
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• 2003

The parasitic effects due to the current blocking layer limit the bandwidth of the semiconductor laser diode. Thus, the parasitic response of various blocking layers was analyzed. The inin type was the best choice for the leakage current reduction and the bandwidth expansion.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.1
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• pp.1-6
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• 2016

In this paper, we introduce the characteristics of a vertical PNP transistor that improves start current by decreasing quiescent current with suppressing the parasitic transistor. In order to suppress the parasitic effect, we designed a vertical PNP transistor which suppresses parasitic PNP transistor by using the "DN+ links" without changing the circuit and made a LDO regulator using a standard IC processor. HFE of the fabricated parasitic PNP transistor decreased from conventional 18 to 0.9. Starting current of the LDO regulator made of the vertical PNP transistor using the improved "DN+ linked" structure is reduced from the conventional starting current of 90mA to 32mA. As the result, we developed a LDO regulator which consumes lower power in the standby state.

• Proceedings of the Optical Society of Korea Conference
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• 2007.07a
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• pp.289-290
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• 2007

We have theoretically derived a electrical model and extracted a parasitic parameters of leakage current in InGaN/GaN light emitting diodes (LEDs). The parasitic parameters of our LED are $R_p=10^{10}{\Omega}$, $I_{0,2}=10^{-17}A$ and $n_2=3.6$, which provide information of leakage current.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.13-16
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• 1998

An anomalous current characteristics which show the superposition of a low current level and high current level at the subthreshold region when SONOSFETs are in memory states were investigated. We have assumed this phenomena were resulted from the effect of parasitic transistors by LOCOS isolation and were modeled to a parallel equivalent circuit of one memory transistor and two parasitic transistors. Theoretical curves are well fitted in measured log I$_{D}$-V$_{G}$ curves independent of channel width of memory devices. The difference between low current level and high current level is apparently decreased with decrease of channel width of devices because parasitic devices dominantly contribute to the current conduction with decrease of channel width of memory devices. As a result, we concluded that the LOCOS isolation has to selectively adopt in the design of process for charge-trap type NVSM.VSM.

• Journal of Power Electronics
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• v.18 no.3
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• pp.892-901
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• 2018

SiC MOSFETs have been used to improve system efficiency in high frequency converters due to their extremely high switching speed. However, this can result in undesirable parasitic oscillations in practical systems. In this paper, models of the key components are introduced first. Then, theoretical formulas are derived to calculate the switching oscillation frequencies after full turn-on and turn-off in clamped inductive circuits. Analysis indicates that the turn-on oscillation frequency depends on the power loop parasitic inductance and parasitic capacitances of the freewheeling diode and load inductor. On the other hand, the turn-off oscillation frequency is found to be determined by the output parasitic capacitance of the SiC MOSFET and power loop parasitic inductance. Moreover, the shifting regularity of the turn-off maximum peak voltage with a varying switching speed is investigated on the basis of time domain simulation. The distortion of the turn-on current is theoretically analyzed. Finally, experimental results verifying the above calculations and analyses are presented.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.3
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• pp.195-203
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• 2020

This paper presents a parasitic inductance reduction design method for the stable driving of GaN HEMT. To reduce the parasitic inductance, we propose a vertical lattice loop structure with multiple loops that is not affected by the GaN HEMT package. The proposed vertical lattice loop structure selects the reference loop and designs the same loop as the reference loop by layering. The design reverses the current direction of adjacent current paths, increasing magnetic flux cancellation to reduce parasitic inductance. In this study, we validate the effectiveness of the parasitic inductance reduction method of the proposed vertical lattice loop structure.

• Tribology and Lubricants
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• v.26 no.5
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• pp.277-282
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• 2010

The purpose of this paper is to study and analysis the failure examples for parasitic current leakage produced in starting system on gasoline engine. It verified the discharge of battery by electric leakage because of internal wiring damage problem for CD auto changer installed in car. Also, it verified the no-stating phenomenon because of deposit forming by chemical reaction of battery fluid between battery post and cable fixing parts. It verified the damage for brush holder and commutator mixing by internal short phenomenon because of brush carbon a particle and engine oil that was flowed into internal of starting motor. It verified the working phenomenon of audio by a point of contact even if the driver turn to "LOCK" position the key.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.6
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• pp.20-32
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• 1997

An optimum parasitic inductance is observed for maximizing the modulation bandwidth of the multiple quantum well (MQW) electro-absorption optical modulator. For 1.1 pF device cpaacitance of the current MQW optical modulator, the optimum parasitic inductances for maximum bandwidth are calculated for different terminating resistors. In ase of 50.ohm. terminating resistor, the 3-dB modulation bandwidth can be increased 45% wider by using the optimum parasitic inductance than nothing parasitic inductance. This calculated optimum inductance can be practically implemented, since the parasitic inductance of bondwires can be accurately analyzed using the method of moments (MoM) and controlled by changing the length and shpae of bondwires.

• Korean Journal of Optics and Photonics
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• v.14 no.4
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• pp.423-428
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• 2003

In a direct modulated semiconductor laser diode. the structural dependence of current blocking layers was studied in view of the leakage current reduction and the bandwidth expansion. To analyze the leakage current and the parasitic effects, the current-voltage derivation characteristics and the subtraction method were used, respectively. It was shown that the‘inin’type current blocking structure might be the best choice for the purpose of the static and dynamic characteristics.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.208-211
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• 1999

Abstract - Electrical characteristics or asymmetric n-MOSFET's with different source and drain geometry are experimently investigated using test structures having various gate width. Saturation drain current and resistance in linear region are estimated by a simple schematic model, which consists of conventional device having parasitic resistor. A comparison of experimental results of symmetric and asymmetric devices gives the parasitic resistance caused by abnormal device structure. The suggested model shows good agreement with the measured drain current for both forward- and reverse-modes.