• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.4
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• pp.859-867
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• 2010

In this paper, we propose some parallel structures of the word-based nonlinear combining functions in word-based stream cipher, high-speed versions of general (bit-based) nonlinear combining functions. Especially, we propose the high-speed structures of popular four kinds in word-based nonlinear combiners using by PS-WFSR (Parallel-Shifting or Parallel-Structured Word-based FSR): m-parallel word-based nonlinear combiner without memory, m-parallel word-based nonlinear combiner with memories, m-parallel word-based nonlinear filter function, and m-parallel word-based clock-controlled function. In addition, we propose an implementation example of the m-parallel word-based DRAGON stream cipher, and determine its cryptographic security and performance.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.2
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• pp.199-203
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• 2012

This paper introduces a simple new procedure approach to determine the permittivity of dielectric slabs. The method uses a parallel plate waveguide which supports a TEM mode. The presence of the dielectric slab placed at the bottom of the waveguide makes the speed of the TEM wave slower. The relationship between the change of the speed and the permittivity of the dielectric slab allows the determination of the permittivity. The relationship is analyzed electromagnetically, and the results of measurements are in good agreement with the analysis.

• International Journal of Internet, Broadcasting and Communication
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• v.12 no.3
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• pp.87-94
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• 2020

Recently, computer hardware is evolving toward increasing the number of computing cores, not increasing the clock speed. In order to use the performance of parallelized hardware to the maximum, the running program must also be parallelized. However, software developers are accustomed to sequential programs, and in most cases, write programs that operate sequentially. They also have a lot of difficulty designing and developing software in parallel. We propose a method to automatically convert a sequential C/C++ program into a parallelized program, and develop a parallelization tool that supports it. It supports open multiprocessing (OpenMP) and parallel patterns library (PPL) as a parallel framework. Perfect automatic parallelization is difficult due to dynamic features such as pointer operation and polymorphism in C/C++ language. This study focuses on verifying the conditions of parallelization rather than focusing on fully automatic parallelization, and providing advice to developers in detail if parallelization is not possible.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.148-151
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• 2005

This paper proposes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that convert redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was designed using a 0.35${\mu}m$ standard CMOS Process. Proposed demultiplexer is achieved an operating speed of 3Gb/s with a supply voltage of 3.3V and with power consumption of 48mW. Designed circuit is limited by maximum operating frequency of process. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 3Gb/s in submicron process of high of operating frequency.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.4 no.4
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• pp.323-328
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• 2003

In this paper new control strategy of series resonant converter system for power supply of communication station is suggested. Frequency controlled series resonant converter system is robust to load variations because it is POSR(Parallel Output Series Resonant: POSR) type. And it provides stable output voltage by changing switching frequency to input voltage variations. Firstly, operation analysis about suggested series resonant converter system was carried. Then simulations using ACSL(Advanced Continuous Simulation Langage) and experiments to actual system were carried to prove characteristics of suggested system.

• Proceedings of the KIEE Conference
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• 1998.07b
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• pp.663-665
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• 1998

The measuring data acquisition methods from local sensor are many kinds of techniques. But, if sampling time is not important and we need data of many sensors it is more resonable to be applied economical system. In this paper, the data acquisition technique is used two RS232C communication signals simultaneously. The one come from computer serial port, and another is signal changed from parallel port. In this case the circuits would be simplification and that communication cable is connected by Parallel instead of Branch connection.

• Proceedings of the IEEK Conference
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• summer
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• pp.325-329
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• 2004

Linear size expanders have been studied in many fields for the practical use, which is possibility to connect large numbers of device chips in parallel communication systems. One major limitation on the efficiency of parallel computer designs has been the prohibitively high cost of parallel communication between processors and memories. Linear size expanders can be used to construct theoretically optimal interconnection networks. In current, the defined constructions have large constant factors, thus rendering them impractical for reasonable sized networks. This paper presents an improvement on constructing concentrators using an $(n,\;k,\;2rs/(r^2-s^2))expander,$ which realizes the reduction of the size in a superconcentrator by a constant factor.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.533-534
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• 2006

This paper presents the architecture design of a high-speed, low-complexity 128-point radix-$2^4$ FFT processor for ultra-wideband (UWB) systems. The proposed high-speed, low-complexity FFT architecture can provide a higher throughput rate and low hardware complexity by using 2-parallel data-path scheme and single-path delay-feedback (SDF) structure. This paper presents the key ideas applied to the design of high-speed, low-complexity FFT processor, especially that for achieving high throughput rate and reducing hardware complexity. The proposed FFT processor has been designed and implemented with the 0.18-m CMOS technology in a supply voltage of 1.8 V. The throughput rate of proposed FFT processor is up to 1 Gsample/s while it requires much smaller hardware complexity.

• ETRI Journal
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• v.37 no.4
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• pp.667-676
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• 2015

The third-party FFT IP cores available in today's markets do not provide the desired speed demands for optical communication. This study deals with the design and implementation of a 256-point Radix-4 100 Gbit/s FFT, where computational steps are reconsidered and optimized for high-speed applications, such as radar and fiber optics. Alternative methods for FFT implementation are investigated and Radix-4 is decided to be the optimal solution for our fully parallel FPGA application. The algorithms that we will implement during the development phase are to be tested on a Xilinx Virtex-6 FPGA platform. The proposed FFT core has a fully parallel architecture with a latency of nine clocks, and the target clock rate is 312.5 MHz.

• Journal of Sensor Science and Technology
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• v.24 no.2
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• pp.107-112
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• 2015

HIGHT is an 64-bit block cipher, which is suitable for low power and ultra-light implementation that are used in the network that needs the consideration of security aspects. This paper presents a parallel key scheduler that generates the whitening keys and subkeys simultaneously for both encryption and decryption processes. We construct the reverse LFSR and key generation blocks to generate the keys for decryption process. Then, the new key scheduler is made by sharing the common logics for encryption and decryption processes to minimize the increase in hardware complexity. From the simulation results, the logic size is increased 1.31 times compared to the conventional HIGHT. However, the performance of HIGHT including the proposed key scheduler can be increased by two times compared to the conventional counterpart.