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Design of a Key Scheduler for Supporting the Parallel Encryption and Decryption Processes of HIGHT

HIGHT 암복호화 병렬 실행을 위한 Key Scheduler 설계

  • Choi, Won-Jung (Div. of of Electronics, Information and Communication Engineering, Kangwon National Unversity) ;
  • Lee, Je-Hoon (Div. of of Electronics, Information and Communication Engineering, Kangwon National Unversity)
  • 최원정 (강원대학교 전자정보통신공학부) ;
  • 이제훈 (강원대학교 전자정보통신공학부)
  • Received : 2015.03.23
  • Accepted : 2015.03.31
  • Published : 2015.03.31

Abstract

HIGHT is an 64-bit block cipher, which is suitable for low power and ultra-light implementation that are used in the network that needs the consideration of security aspects. This paper presents a parallel key scheduler that generates the whitening keys and subkeys simultaneously for both encryption and decryption processes. We construct the reverse LFSR and key generation blocks to generate the keys for decryption process. Then, the new key scheduler is made by sharing the common logics for encryption and decryption processes to minimize the increase in hardware complexity. From the simulation results, the logic size is increased 1.31 times compared to the conventional HIGHT. However, the performance of HIGHT including the proposed key scheduler can be increased by two times compared to the conventional counterpart.

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References

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