Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)
- 2005.05a
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- Pages.148-151
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- 2005
Design of a High Speed and Low Power CMOS Demultiplexer Using Redundant Multi-Valued Logic
Redundant Multi-Valued Logic을 이용한 고속 및 저전력 CMOS Demultiplexer 설계
Abstract
This paper proposes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that convert redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was designed using a 0.35