• 한국정보통신학회논문지
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• 제14권4호
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• pp.859-867
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• 2010

본 논문에서는 일반적인 비트기반의 비선형 결합함수를 고속화하기 위하여 워드기반 스트림 암호에서 적용될 워드기반 비선형 결합함수 구조를 제안하였다. 특히, 워드기반 병렬구조를 갖는 PS-WFSR을 제안하였고, 이를 활용하여 비트 기반 비선형 결합함수를 고속화시킨 4가지 형태의 워드기반 병렬형 비선형 결합함수를 다음과 같이 제안하였다. m-병렬 워드기반 비메모리 비선형 결합함수, m-병렬 워드기반 메모리 비선형 결합함수, m-병렬 워드기반 비선형 필터함수, m-병렬 워드기반 클럭조절형 함수를 제안하였고, 마지막으로 m-병렬 워드기반 DRAGON의 병렬 구조를 통하여 그 성능을 분석하였다.

• 한국인터넷방송통신학회논문지
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• 제12권2호
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• pp.199-203
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• 2012

평행판 도파관에 진행하는 TEM mode를 이용한 평판형 유전체의 유전율을 측정하는 방식을 소개한다. 이는 양 옆이 열린 구조적 장점으로 실험 절차 및 측정 샘플의 가공이 매우 간편한 장점이 있다. 샘플의 유무에 따라 변화하는 도파관 내에서 전파하는 TEM mode의 위상 속도의 차이를 전자기적으로 해석하였고 이를 이용하여 유전체판의 유전율을 측정하였으며, 샘플에 대한 측정 결과는 기존에 알려진 유전율과 일치하였다.

• International Journal of Internet, Broadcasting and Communication
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• 제12권3호
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• pp.87-94
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• 2020

Recently, computer hardware is evolving toward increasing the number of computing cores, not increasing the clock speed. In order to use the performance of parallelized hardware to the maximum, the running program must also be parallelized. However, software developers are accustomed to sequential programs, and in most cases, write programs that operate sequentially. They also have a lot of difficulty designing and developing software in parallel. We propose a method to automatically convert a sequential C/C++ program into a parallelized program, and develop a parallelization tool that supports it. It supports open multiprocessing (OpenMP) and parallel patterns library (PPL) as a parallel framework. Perfect automatic parallelization is difficult due to dynamic features such as pointer operation and polymorphism in C/C++ language. This study focuses on verifying the conditions of parallelization rather than focusing on fully automatic parallelization, and providing advice to developers in detail if parallelization is not possible.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 심포지엄 논문집 정보 및 제어부문
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• pp.148-151
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• 2005

This paper proposes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that convert redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was designed using a 0.35${\mu}m$ standard CMOS Process. Proposed demultiplexer is achieved an operating speed of 3Gb/s with a supply voltage of 3.3V and with power consumption of 48mW. Designed circuit is limited by maximum operating frequency of process. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 3Gb/s in submicron process of high of operating frequency.

• 한국산학기술학회논문지
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• 제4권4호
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• pp.323-328
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• 2003

본 논문에서는 통신 기지국용 전원으로 사용할 수 있는 직렬 공진형 컨버터 시스템의 새로운 제어방식을 제안하였다. 주파수 제어 직렬 공진형 컨버터 시스템은 병렬 출력 직렬 공진(Parallel Output Series Resonant: POSR)형태이기 때문에 부하변동에 강인하다. 또한 스위칭 주파수를 제어함으로써 입력전압의 변화에도 안정된 출력을 제공한다. 실제 시스템 제작에 앞서 제안된 병렬 출력 직렬 공진형 컨버터 시스템의 분석을 하였고 ACSL(Advanced Continuous Simulation Language)을 이용한 모의실험을 하였다. 또한 실제의 시스템을 제작 및 실험을 통하여 시스템 특성을 확인하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 B
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• pp.663-665
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• 1998

The measuring data acquisition methods from local sensor are many kinds of techniques. But, if sampling time is not important and we need data of many sensors it is more resonable to be applied economical system. In this paper, the data acquisition technique is used two RS232C communication signals simultaneously. The one come from computer serial port, and another is signal changed from parallel port. In this case the circuits would be simplification and that communication cable is connected by Parallel instead of Branch connection.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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• pp.325-329
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• 2004

Linear size expanders have been studied in many fields for the practical use, which is possibility to connect large numbers of device chips in parallel communication systems. One major limitation on the efficiency of parallel computer designs has been the prohibitively high cost of parallel communication between processors and memories. Linear size expanders can be used to construct theoretically optimal interconnection networks. In current, the defined constructions have large constant factors, thus rendering them impractical for reasonable sized networks. This paper presents an improvement on constructing concentrators using an $(n,\;k,\;2rs/(r^2-s^2))expander,$ which realizes the reduction of the size in a superconcentrator by a constant factor.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.533-534
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• 2006

This paper presents the architecture design of a high-speed, low-complexity 128-point radix-$2^4$ FFT processor for ultra-wideband (UWB) systems. The proposed high-speed, low-complexity FFT architecture can provide a higher throughput rate and low hardware complexity by using 2-parallel data-path scheme and single-path delay-feedback (SDF) structure. This paper presents the key ideas applied to the design of high-speed, low-complexity FFT processor, especially that for achieving high throughput rate and reducing hardware complexity. The proposed FFT processor has been designed and implemented with the 0.18-m CMOS technology in a supply voltage of 1.8 V. The throughput rate of proposed FFT processor is up to 1 Gsample/s while it requires much smaller hardware complexity.

• ETRI Journal
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• 제37권4호
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• pp.667-676
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• 2015

The third-party FFT IP cores available in today's markets do not provide the desired speed demands for optical communication. This study deals with the design and implementation of a 256-point Radix-4 100 Gbit/s FFT, where computational steps are reconsidered and optimized for high-speed applications, such as radar and fiber optics. Alternative methods for FFT implementation are investigated and Radix-4 is decided to be the optimal solution for our fully parallel FPGA application. The algorithms that we will implement during the development phase are to be tested on a Xilinx Virtex-6 FPGA platform. The proposed FFT core has a fully parallel architecture with a latency of nine clocks, and the target clock rate is 312.5 MHz.

• 센서학회지
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• 제24권2호
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• pp.107-112
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• 2015

HIGHT is an 64-bit block cipher, which is suitable for low power and ultra-light implementation that are used in the network that needs the consideration of security aspects. This paper presents a parallel key scheduler that generates the whitening keys and subkeys simultaneously for both encryption and decryption processes. We construct the reverse LFSR and key generation blocks to generate the keys for decryption process. Then, the new key scheduler is made by sharing the common logics for encryption and decryption processes to minimize the increase in hardware complexity. From the simulation results, the logic size is increased 1.31 times compared to the conventional HIGHT. However, the performance of HIGHT including the proposed key scheduler can be increased by two times compared to the conventional counterpart.