• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.67-72
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• 2010

In this paper, a design optimization of ball grid array packaging geometry is studied based on the Taguchi method, which allowed robust design by considering the variance of the input parameters during the optimization process. Molding compound and substrate were modeled as viscoelastic, and finite element analyses were performed to calculate the strain energy densities of the eutectic solder balls. Six quality factors of the dimensions of the packaging geometry were chosen as control factors. After performing noise experiments to determine the dominant factors, main experiments were conducted to find the optimum packaging geometry. Then the strain energy densities between the original and optimized geometries were compared. It was found that the effects of the packaging geometry on the solder ball reliability were significant, and more than 40% of the strain energy density was reduced by the geometry optimization.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.4
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• pp.117-123
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• 2015

In order to develop stretchable substrate technology for stretchable devices, locally stiffness-variant stretchable substrates were processed with two polydimethylsiloxane elastomers of different stiffnesses and their deformation behavior was characterized. Low-stiffness substrate matrix and embedded high-stiffness island of the stretchable substrate were formed by using Dragon Skin 10 of the elastic modulus of 0.09 MPa and Sylgard 184 of the elastic modulus of 2.15 MPa, respectively. A stretchable substrate was fabricated to a configuration of 6.5 cm length, 0.4 cm thickness, and 2.5 cm width. The elastic modulus of a stretchable substrate was increased from 0.09 MPa to 0.13~0.33 MPa by embedding a Sylgard 184 island of 1 cm width and 1~6 cm length into the center part of the Dragon Skin 10 substrate matrix. The elastic modulus of a stretchable substrate was improved to 0.16~0.2 MPa by embedding a Sylgard 184 island of 4 cm length and 0.5~1.5 cm width and to 0.1421~0.154 MPa by embedding a Sylgard 184 island of 2 cm length and 0.5~1.5 cm width. With increasing the tensile strain of a stretchable substrate, deformation restriction of the locally stiffness-variant Sylgard 184 island was further enhanced due to substantial increase in the strength difference between Sylgard 184 and Dragon 10 at large strain.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.3
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• pp.1-6
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• 2016

The Internet of Things (IoT) is a new technology paradigm demanding one packaged system of various semiconductor and MEMS devices. Therefore, the development of electronic packaging technology with very high connectivity is essential for successful IoT applications. This paper discusses both fan-out wafer level packaging (FOWLP) and 3D stacking technologies to achieve the integrattion of heterogeneous devices for IoT. FOWLP has great advantages of high I/O density, high integration, and design flexibility, but ultra-fine pitch redistribution layer (RDL) and molding processes still remain as main challenges to resolve. 3D stacking is an emerging technology solving conventional packaging limits such as size, performance, cost, and scalability. Among various 3D stacking sequences wafer level via after bonding method will provide the highest connectivity with low cost. In addition substrates with ultra-thin thickness, ultra-fine pitch line/space, and low cost are required to improve system performance. The key substrate technologies are embedded trace, passive, and active substrates or ultra-thin coreless substrates.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.209-209
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• 2007

Passive Device는 RF Circuit을 제작할 때 많은 면적을 차지하고 있으며 이를 감소시키기 위해 여러 연구가 진행되고 있다. 최근 SoP-L 공정을 이용한 많은 연구가 진행되고 있는데 PCB 제작에 이용되는 일반적인 재료와 공정을 그대로 이용함으로써 개발 비용과 시간 면에서 많은 장점을 가지기 때문이다. SoP-L의 또 하나 장점은 다층구조를 만들기가 용이하다는 점이다. 각 층 간에는 Via를 사용하여 연결하게 되는데, RF Circuit은 회로의 구조와 물성에 따라 특성이 결정되며, 그만큼 Via를 썼을 때 그 영향을 생각해야 한다. 본 연구에서는 multi-layer LCP substrate에 다수의 Via를 chain 구조로 형성하여 전기적 특성을 확인하였다. Via가 70um 두께의 substrate를 관통하면서 상층과 하층의 Conductor을 연속적으로 연결하게 된다. 이 구조의 Resistance와 Insertion Loss를 측정하여, Via의 크기 별 수율과 평균적인 Resistance, RF 계측기로 재현성을 확인하였다. 이를 바탕으로 공정에서의 안정성을 확보하고 Via의 크기와 도금방법에 의한 RF Circuit에서의 영향을 파악하여, 앞으로의 RF Device 개발에 도움이 될 것으로 기대한다. 특히 유기물을 이용한 다층구조의 고주파 RF Circuit에 Via를 적용할 때의 영향을 설계에서부터 고려할 수 있는 자료가 될 것이다.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.3
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• pp.19-26
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• 2017

Stretchable deformation-resistance characteristics of Au, Pt, and Cu films were measured for the stretchable packaging structure where a parylene F was used as an intermediate layer between a PDMS substrate and a metal thin film. The 150 nm-thick Au and Pt films, sputtered on the parylene F-coated PDMS substrate, exhibited the initial resistances of $1.56{\Omega}$ and $5.53{\Omega}$, respectively. The resistance increase ratios at 30% tensile strain were measured as 7 and 18 for Au film and Pt film, respectively. The 150 nm-thick Cu film, sputtered on the parylene F-coated PDMS substrate, exhibited a very poor stretchability compared to Au and Pt films. Its resistance was initially $18.71{\Omega}$, rapidly increased with applying tensile deformation, and finally became open at 5% tensile strain.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.4
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• pp.35-41
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• 2016

Ceramic-metal based high power LED array package was developed via thick film LTCC technology using a glass-ceramic insulation layer and a silver conductor patterns directly printed on the aluminum heat sink substrate. The thermal resistance measurement using thermal transient tester revealed that ceramic-metal base LED package exhibited a superior heat dissipation property to compare with the previously known packaging method such as FR-4 based MCPCB. A prototype LED package sub-module with 50 watts power rating was fabricated using a ceramic-metal base chip-on-a board technology with minimized camber deformation during heat treatment by using partially covered glass-ceramic insulation layer design onto the aluminum heat spread substrate. This modified circuit design resulted in a camber-free packaging substrate and an enhanced heat transfer property compared with conventional MCPCB package. In addition, the partially covered design provided a material cost reduction compared with the fully covered one.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.4
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• pp.435-442
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• 2004

This paper presents a hermetic MEMS on-chip package bonded by a closed-loop AuSn solder-line. We design three different package specimens, including a substrate heated specimen without interconnection-line (SHX), a substrate heated specimen with interconnection-line (SHI) and a locally heated specimen with interconnection-line (LHI). Pressurized helium leak test has been carried out for hermetic seal evaluation in addition to the critical pressure test for bonding strength measurement. Substrate heating method (SHX, SHI) requires the bonding time of 40min. at 400min, while local heating method (LHI) requires 4 min. at the heating power of 6.76W. In the hermetic seal test. SHX, SHI and LHI show the leak rates of 5.4$\pm$6.7${\times}$$^{-10}$ mbar-l/s, 13.5$\pm$9.8${\times}$$^{-10}$ mbar-l/s and 18.5$\pm$9.9${\times}$$^{-10}$ mbar-l/s, respectively, for an identical package chamber volume of 6.89$\pm$0.2${\times}$$^{-10}$. In the critical pressure test, no fracture is found in the bonded specimens up to the applied pressure of 1$\pm$0.1MPa, resulting in the minimum bonding strength of 3.53$\pm$0.07MPa. We find that the present on-chip packaging using a closed AuSn solder-line shows strong potential for hermetic MEMS packaging with interconnection-line due to the hermetic seal performance and the shorter bonding time for mass production.

• Journal of the Semiconductor & Display Technology
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• v.5 no.2 s.15
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• pp.33-36
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• 2006

Many issues arose to use the Pb-free solder as adhesive materials in MEMS ICs and packaging. Then this study for easy and simple sealing method using adhesive materials was carried out to maintain hermetic characteristic in MEMS Package. In this study, Hermetic characteristic using negative PR (XP SU-8 3050 NO-2) as adhesive at the interface of Si test coupon/glass substrate and Si test coupon/LTCC substrate was examined. For experiment, the dispenser pressure was 4 MPa and the $200\;{\mu}m{\Phi}$ syringe nozzle was used. 3.0 mm/sec as speed of dispensing and 0.13 mm as the gap between Si test coupon and nozzle was selected to machine condition. 1 min at $65^{\circ}C$ and 15 min at $95^{\circ}C$ as Soft bake, $200\;mj/cm^2$ expose in 365 nm wavelength as UV expose, 1 min at $65^{\circ}C$ and 6 min at $95^{\circ}C$ as Post expose bake, 60 min at $150^{\circ}C$ as hard bake were selected to activation condition of negative PR. Hermetic sealing was achieved at the Si test coupon/ glass substrate and Si test coupon/LTCC substrate. The leak rate of Si test coupon/glass substrate was $5.9{\times}10^{-8}mbar-l/sec$, and there was no effect by adhesive method. The leak rate of Si test coupon/LTCC substrate was $4.9{\times}10^{-8}mbar-l/sec$, and there was no effect by dispensing cycle. Better leak rate value could be achieved to use modified substrate which prevent PR flow, to increase UV expose energy and to use system that controls gap automatically with vision.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.3
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• pp.61-67
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• 2020

In this paper, we calculated the warpage of bare substrates and chip attached substrates by using FEM (Finite Element Method), and compared and analyzed the effect of the chips' attachment on warpage. Also, the effects of layer thickness of substrates for reducing warpage were analyzed and the conditions of layer thickness were analyzed by signal-to-noise ratio of Taguchi method. According to the analysis results, the direction of warpage pattern in substrates can change when chips are attached. Also, the warpage decreases as the difference in the CTE (coefficient of thermal expansion) between the top and bottom of the package decreases and the stiffness of the package increases after chips are loaded. In addition, according to the impact analysis of design parameters on substrates where chips are not attached, in order to reduce warpage, the inner layers of the circuit layer Cu1 and Cu4 has be controlled first, and then concentrated on the thickness of the solder resist on the bottom side and the thickness of the prepreg layer between Cu1 and Cu2.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.4
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• pp.31-39
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• 2021

In this paper, warpage analysis that separates PCB for PoP (Package on Package) into unit and substrate using FEM (Finite Element Method), analysis of the effect of layer thickness on warpage, and SN (Signal-to-Noise) ratio by Taguchi method was carried. According to the analysis result, the contribution of the circuit layer on warpage was very high in the unit PCB, and the contribution of the outer layer was particularly high. On the other hand, the substrate PCB had a high influence of the circuit layer on warpage, but it was relatively low compared to the unit PCB, and the influence of the solder resist was rather increased. Therefore, considering the unit PCB and the substrate PCB at the same time, it is desirable to design the PCB for PoP layer-by-layer structure so that the outer and inner circuit layers are thick, the top solder resist is thin, and the thickness of the bottom solder resist is between 5 ㎛ and 25 ㎛.