• Electrical & Electronic Materials
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• v.8 no.6
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• pp.737-743
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• 1995

Two step RTD(Rapid Thermal Diffussion) of P into silicon wafer using tungsten halogen lamp was used to fabricated very shallow n$^{+}$p junction. 1st RTD was performed in the temperature range of 800.deg. C for 60 see and the heating rate was in the 50.deg. C/sec. Phosphrous solid source was transfered on the silicon surface. 2nd RTD process was performed in the temperature range 1050.deg. C, 10sec. Using 2 step RTD we can obtain a shallow junction 0.13.mu.m in depth. After RTD, the Ti-silicide process was performed by the two step RTA(Rapid Thermal Annealing) to reduced the electric resistance and to improve the n$^{+}$p junction diode. The titanium thickness was 300.angs.. The condition of lst RTA process was 600.deg. C of 30sec and that of 2nd RTA process was varied in the range 700.deg. C, 750.deg. C, 800.deg. C for 10sec-60sec. After 2 step RTA, sheet resistance was 46.ohm../[]. Ti-silicide n+p junction diode was fabricated and I-V characteristics were measured.red.

• Proceedings of the KIEE Conference
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• 1989.07a
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• pp.662-666
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• 1989

Pure mono Silane(Purity: 99.99%) was used as a thin film source and [$SiH_4$ + $H_2$ (5%)] + [$PH_3$ + $H_2$(0.05%)] mixed dilute gas was used for p-n junction diode. The substrate was P-type silicon wafer (p=$3{\Omega}$ cm) with the direction (100). The crystalline qualities of deposited thin film were investigated by the X-ray diffraction, RHEED and TED patterns and the voltampere characteristics of p-n junction diode was identified by I-V curve.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.11
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• pp.908-913
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• 2000

CoSi$_2$/p+/n diodes(bilayer diodes) were fabricated by using epitaxial CoSi$_2$grown from Co/Ti bilayer as a diffusion source. The I-V characteristics of p+/n diodes were measured and compared with those of diode made from Co monolayer (monolayer diode). Monolayer diodes showed typical p+n junction characteristics with the leakage current of as low as 10$^{-12}$ A and forward current 6-orders higher than the leakage current, when drive-in annealed at 90$0^{\circ}C$ for 20 sec.. On the other hand, bilayer diodes showed the Schottky-like behaviors with forward currents rather higher than those of monolyer diodes, but with too high leakage currents, when drive-in annealed at $700^{\circ}C$ or higher. However, when the annealing temperature was lowered to $700^{\circ}C$ and annealing time was increased to 60 sec., the leakage current was reduced to 10$^{-11}$ A and thus sho3wed typical diode characteristics. The high leakage currents for diodes annealed at $700^{\circ}C$ or higher was attributed to Shannon contacts formed due to unremoved Co-Ti-Si precipitates. But when annealed at 50$0^{\circ}C$, B ions diffused in the direction of the surface layer, and thus the leakage currents were reduced by removing Shannon contacts.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.43-51
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• 2006

80-nm self-aligned n-and p-channel I-MOS devices were demonstrated by using a novel fabrication method featuring double sidewall spacer, elevated drain structure and RTA process. The fabricated devices showed a normal transistor operation with extremely small subthreshold swing less than 12.2 mV/dec at room temperature. The n- and p-channel I-MOS devices had an ON/OFF current of 394.1/0.3 ${\mu}A$ and 355.4/8.9 ${\mu}A$ per ${\mu}m$, respectively. We also investigated some critical issues in device design such as the junction depth of the source extension region and the substrate doping concentration.

• Transactions on Electrical and Electronic Materials
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• v.3 no.2
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• pp.10-15
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• 2002

In this paper, the electrical characteristics of fabricated p+-n junction diode are demonstrated and interpreted with different theoretical calculations. Dopants distribution by boron ion implantation on silicon wafer were simulated with TRIM-code and ICECaEM simulator. In order to make electrical activation of implanted carriers, thermal annealing treatments are carried out by RTP method for 1min. at $1000^{circ}C$ under inert $N_2$ gas condition. In this case, profiles of dopants distribution before and after heat treatments in the substrate are observed from computer simulations. In the I-V characteristics of fabricated diodes, an analytical description method of a new triangular junction model is demonstrated and the results with calculated triangular junction are compared with measured data and theoretical calculated results of abrupt junction. Forward voltage drop with new triangular junction model is lower than the case of abrupt junction model. In the C-V characteristics of diode, the calculated data are compared with the measured data. Another I-V characteristics of diodes are measured after proton implantation in electrical isolation method instead of conventional etching method. From the measured data, the turn-on characteristics after proton implantation is more improved than before proton implantation. Also the C-V characteristics of diode are compared with the measured data before proton implantation. From the results of measured data, reasonable deviations are showed. But the C-V characteristics of diode after proton implantation are deviated greatly from the calculated data because of leakage currents in defect regions and layer shift of depletion by proton implantation.

• 한국신재생에너지학회:학술대회논문집
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• 2010.06a
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• pp.62.2-62.2
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• 2010

박막 실리콘 태양 전지는 저가격화 및 대량생산, 대면적화에 유리하다는 장점을 가지고 있다. 단점으로 지적되는 낮은 효율을 극복하기 위해 광흡수층의 밴드갭이 서로 다른 두 개 이상의 박막을 적층하여, 넓은 파장 대역의 빛을 효과적으로 흡수함으로써 광변환 효율을 올리기 위한 많은 연구가 이루어지고 있다. 서로 다른 밴드갭의 광흡수층을 가진 p-i-n 구조를 다중 적층하여 고효율의 태양 전지를 제작하기 위해서는 n-도핑층과, p-도핑층 간에 전자와 정공이 빠르게 재결합할 수 있는 터널 접합(Tunnel Recombination Junction)의 형성이 필수적이며, 이때 광손실이 최소화되도록 해야한다. 만약 터널 접합이 적절하게 형성되지 않으면 결합되지 않은 전자와 정공이 도핑층 사이에 쌓이게 되고, 도핑층 사이의 저항 증가로 태양 전지의 광변환 효율은 크게 하락한다. 이번 연구에서는 터널 접합이 잘 이루어지게 하기 위한 n-도핑층 및 p-도핑층 박막의 특성과, 터널 접합의 특성에 따른 적층형 태양 전지의 광효율 변화를 확인하였다. 광흡수층 및 도핑층은 TCO($SnO_2:F$, Asahi) 유리 기판 위에 PECVD를 사용하여 p-i-n 구조로 RF Power 조건에서 증착되었고, ${\mu}c$-Si 광흡수층의 경우에는 VHF Power 조건에서 증착되었다. 광흡수층이 a-Si/${\mu}c$-Si의 구조를 가지는 이중 접합 태양 전지에서 ${\mu}c$-Si n-도핑층/${\mu}c$-Si p-도핑층 사이의 터널 접합 실험 결과 n-도핑층 및 p-도핑층의 결정화도와 도핑 농도를 조절하여 터널 접합의 저항을 최소화했고, 터널 접합 특성이 이중 접합 셀의 광효율 특성과 유사한 경향을 보임을 확인하였다. 광흡수층이 a-Si/a-SiGe/${\mu}c$-Si의 구조를 가지는 삼중 접합 태양 전지 실험의 경우 a-Si과 a-SiGe 광흡수층 사이에 ${\mu}c$-Si n-도핑층/${\mu}c$-Si p-도핑층/a-SiC p-도핑층의 구조를 적용하여 터널 접합을 형성하였으며, ${\mu}c$-Si p-도핑층의 두께 및 박막 특성을 개선하여 광손실이 최소화된 터널 접합을 구현하였고, 삼중 접합 태양 전지에 적용되었다.

• Journal of Information Display
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• v.8 no.2
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• pp.20-24
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• 2007

Efficient white organic light-emitting diodes are fabricated with the blue and red electroluminescent (EL) units electrically connected in a stacked tandem structure by using a transparent doped organic p/n junction. The blue and red EL units consist of the light-emitting layer of 1,4-bis(2,2-diphenyl vinyl)benzene (DPVBi) and 4-dicyanomethylene-2-methyl-6-[2-(2,3,6,7-tetrahydro-1H,5H-benzo[i,j] quinolizin-8-yl)vinyl]-4H-pyran) (DCM2) doped tris(8-hydroxyquinoline) aluminum $(Alq_3)$, respectively. The organic p-n junction consists of ${\alpha}-NPD$ doped with $FeCl_3$ (15 % by weight ratio) and $Alq_3$ doped with Li (10 %). The EL spectra exhibit two peaks at 448 and 606 nm, resulting in white light-emission with the Commission Internationale d'Eclairage (CIE) chromaticity coordinates of (0.36, 0.24). The tandem device shows the quantum efficiency of about 2.2 % at a luminance of 100 $cd/m^2$, higher than individual blue and red EL devices.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.1
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• pp.51-54
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• 2009

Transparent Cuprous oxide film was deposited by rapid thermal oxidation (RTO) of Cu at $500^{\circ}C$/45s condition on textured single-crystal n-Si substrate to form $Cu_2O$/n-Si heterojunction photodiode. The Hall effect measurements for the $Cu_2O$ films showed a p-type conductivity. The photovoltaic and electrical properties of the junction at room temperature were investigated without any post-deposition annealing. I-V characteristics revealed that the junction has good rectifying properties. The C-V data showed abrupt junction and a built-in potential of 1 V. The photodiode showed good stability and high responsivity in the visible at three regions; 525 nm, 625-700 nm, and 750nm denoted as regions A, B, and C, respectively.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2007.06a
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• pp.109-112
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• 2007

In this paper we describe a robust method of improving precision in monitoring high energy ion implantation processes. Ion implant energy accuracy was measured in the device manufacturing process using an unpatterned implanted layer on an intrinsic p-type silicon wafer. To increase Rs sensitivity to energy at the well implant process, a PN junction structure was formed by P-well and deep N-well implants into the p-type Si wafer. It was observed that the depletion layer formed by the PN junction was very sensitive to energy variation of the well implant. Conclusively, it can be recommended to monitor well implant processes using the Rs measurement method described herein, i.e., a PN junction diode structure since it shows excellent Rs sensitivity to variation caused by energy difference at the well implant step.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.315.1-315.1
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• 2014

The use of cellulose papers has recently attracted much attention in various device applications owing to their natural advantageous properties of earth's abundance, bio-friendly, large-scale production, and flexibility. Conventional metal oxides with novel structures of nanorods, nanospindles, nanowires and nanobelts are being developed for emerging electronic and chemical sensing applications. In this work, both ZnO (n-type) nanorod arrays (NRAs) and CuO (p-type) nanospindles (NSs) were synthesized on cellulose papers and the p-n junction property was investigated using the electrode of indium tin oxide coated polyethylene terephthalate film. To synthesize ZnO and CuO nanostructures on cellulose paper, a simple and facile hydrothermal method was utilized. First, the CuO NSs were synthesized on cellulose paper by a simple soaking process, yielding the well adhered CuO NSs on cellulose paper. After that, the ZnO NRAs were grown on CuO NSs/cellulose paper via a facile hydrothermal route. The as-grown ZnO/CuO NSs on cellulose paper exhibited good crystalline and optical properties. The fabricated p-n junction device showed the I-V characteristics with a rectifying behaviour.