• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.3
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• pp.233-236
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• 2002

Some measures are provided for the optimum design of specific on-resistance $R_{on}$ and breakdown-voltage $V_B$ of interdigitated CB (Composite Buffer) MOSFET, including introducing opposite type impurity into the P region near the $N_＋$contact, separating P region from N region with an oxide film, and a groove in the N region near the $P_＋$ contact. The new relationship between the $R_{on}$ and $V_B$, which proved by numerical device simulation, are more exact and minute than the qualitative results before.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.695-697
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• 2013

In this paper, temperature sensing circuit using by MOS is proposed. It produces the voltage as output and is applicable for the internal IC temperature measurement. It is designed by two current mirrors using MOS to implement the IC in the CMOS fabrication and is applicable for the various applications. It operates in two mode, temperature mode and sleep mode. From the simulation results, output voltage is measured from 0V to 1.2V by sweeping $0^{\circ}C{\sim}125^{\circ}C$ in temperature mode and output current flows under 100pA in sleep mode.

• Journal of IKEEE
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• v.25 no.2
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• pp.356-361
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• 2021

Super Junction structure is the proposed structure to minimize the Trade-off phenomenon of power devices. Super Junction can have On-resistance(Ron) characteristics as less as five times than conventional structure. There are process methods that Multi-Epi and Deep-Trench of Super Junction structure. The reason for this is that Deep-Trench process is known to be a relatively difficult manufacturing method because it is easy to form a P-Pillar by burying impurities on top of a silicon substrate through a Deep-Trench process. However, the structure created by the Deep-Trench process has low On-resistance and high breakdown voltage, showing better efficiency. In this paper, we suggested a novel method in the process and designed structure with Charge Balance theory.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.6
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• pp.345-348
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• 2017

In this work, static characteristics of 4H-SiC SJ-ACCUFETs were obtained by adjusting the p-pillar region. The structure of this SJ-ACCUFET was designed by using a two-dimensional simulator. The static characteristics of SJ-ACCUFET, such as the breakdown voltages, on-resistance, and figure of merits, were obtained by varying the p-pillar doping concentration from $1{\times}10^{15}cm^{-3}$ to $5{\times}10^{16}cm^{-3}$ and the thickness from $0{\mu}m$ to $9{\mu}m$. The doping concentration and the thickness of p-pillar region are closely related to the break down voltage and on-resistance and threshold voltages. Hence a silicon carbide SJ-ACCUFET structure with highly intensified breakdown voltages and low on-resistances with good figure of merits can be achieved by optimizing the p-pillar thickness and doping concentration.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.391-392
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• 2013

반도체 집적회로의 고집적화 및 고성능화를 위한 기본 소자(MOSFET)의 미세화 및 단위공정의 물리적 한계를 극복하기 위해 기존의 Top-down 방식에서 buttom-up 방식의 공정에 대한 연구가 진행되고 있다. 그 중 nanoparticles를 이용한 나노소자 제작 연구가 이루어지고 있다. 하지만 이러한 nanoparticles를 이용한 나노소자의 제작에 있어서 원하는 위치에 nanoparticles를 배열하고 정렬하는데 어려움을 겪고 있다. 이 문제를 해결하기 위해서 자기조립 특성을 가지고 있는 DNA분자와 기능화를 통하여 표면에 positive charge를 띄고있는 Gold nanoparticles를 상호결합 시키는 실험을 하였다. Au-DNA nanowire는 backbone에 있는 phosphate부분에서 negative charge를 띠고 있는 DNA와 positive charge를 띠고 있는 Gold nanoparticles가 결합하는 원리로 형성된다. 그렇지만 Gold particles를 표면이 아닌 DNA에만 붙이는 것은 아직 해결해야 할 부분으로 남아있다. 본 연구에서는 이 문제를 해결하기 위하여 pH 조절을 통하여 기능화된 Gold particles의 charge의 변화를 주고 이를 Zeta potential 측정기로 측정한 후에 이 particles와 DNA를 결합시켜서 FE-SEM과 AFM 으로 확인하는 실험을 하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.11
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• pp.939-942
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• 2007

We investigated the characteristics of UTB-SOI pMOSFETs with SOI thickness($T_{SOI}$) ranging from 10 nm to 1 nm and evaluated the dependence of electrical characteristics on the silicon surface orientation. As a result, it is found that the subthreshold characteristics of (100)-surface UTB-SOI pMOSFETs were superior to (110)-surface. However, the hole mobility of (110)-surface were larger than that of (100)-surface. Especially, the enhancement of effective hole mobility at the effective field of 0.1 MV/cm was observed from 3-nm to 5-nm SOI thickness range.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.146-146
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• 2010

일반적인 MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor)은 소스와 드레인의 형성을 위해서 불순물을 주입하고 고온의 열처리 과정을 거치게 된다. 이러한 고온의 열처리 과정 때문에 녹는점이 낮은 메탈게이트와 게이트 절연막으로의 high-k 물질의 사용에 제한을 받게된다. 이와 같은 문제점을 보완하기 위해서 소스와 드레인 영역에 불순물 주입공정 대신에 금속접합을 이용한 Schottky Barrier Tunnel Transistor (SBTT)가 제안되었다. SBTT는 $500^{\circ}C$ 이하의 저온에서 불순물 도핑없이 소스와 드레인의 형성이 가능하며 실리콘에 비해서 수십~수백배 낮은 면저항을 가지며, 단채널 효과를 효율적으로 제어할 수 있는 장점이 있다. 또한 고온공정에 치명적인 단점을 가지고 있는 high-k 물질의 적용 또한 가능케한다. 본 연구에서는 p-type SOI (Silicon-On-Insulator) 기판을 이용하여 Pt-silicide 소스와 드레인을 형성하고 전기적인 특성을 분석하였다. 또한 본 연구에서는 기존의 sidewall을 사용하지 않는 새로운 구조를 적용하여 메탈게이트의 사용을 최적화하였고 게이트 절연막으로써 실리콘 옥사이드를 스퍼터링을 이용하여 증착하였기 때문에 저온공정을 성공적으로 수행할 수 있었다. 이러한 게이트 절연막은 열적으로 형성시키지 않고도 70 mv/dec 대의 우수한 subthreshold swing 특성을 보이는 것을 확인하였고, $10^8$정도의 높은 on/off current ratio를 갖는 것을 확인하였다.

• Journal of Satellite, Information and Communications
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• v.10 no.4
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• pp.1-5
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• 2015

The ESD(electrostatic discharge) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlled rectifier(NSCR_PPS) device with different partial p-well(PPW) structure was discussed for high voltage I/O applications. A conventional NSCR_PPS standard device shows typical SCR-like characteristics with low on-resistance, low snapback holding voltage and low thermal breakdown voltage, which may cause latch-up problem during normal operation. However, our proposed NSCR_PPS devices with modified PPW_PGM(primary gate middle) and optimal CPS(counter pocket source) implant demonstrate the stable ESD protection performance with high latch-up immunity.

• Journal of Satellite, Information and Communications
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• v.9 no.2
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• pp.12-17
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• 2014

In this paper, modified EDNMOS device with DPS (double polarity source) structure are suggested to realize stable and robust ESD (electrostatic discharge) protection performance of high voltage operating microchip. This DPS structure inserts the P+ diffusion layer on N+ source side, which in intended to block lateral extension of the electron rich region from N+ source side. Based on our simulation results, the inserted P+ diffusion layer effectively prevents the formation of deep electron channeling induced by high electron injection. As a result, our proposed DPS_EDNMOS devices could overcome the double snapback effect of conventional Std_EDNMOS device.

• Journal of Satellite, Information and Communications
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• v.9 no.4
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• pp.63-68
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• 2014

Electrostatic Discharge(ESD) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlled rectifier(NSCR_PPS) device with different partial p-well(PPW) structure was discussed for high voltage I/O applications. A conventional NSCR_PPS standard device shows typical SCR-like characteristics with low on-resistance, low snapback holding voltage and low thermal breakdown voltage, which may cause latch-up problem during normal operation. However, our proposed NSCR_PPS devices with modified PPW demonstrate the stable ESD protection performance with high latch-up immunity.