• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.170-170
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• 2010

Thin-film transistors (TFT) have become the key components of electronic and optoelectronic devices. Most conventional thin-film field-effect transistors in display applications use an amorphous or polycrystal Si:H layer as the channel. This silicon layers are opaque in the visible range and severely restrict the amount of light detected by the observer due to its bandgap energy smaller than the visible light. Therefore, Si:H TFT devices reduce the efficiency of light transmittance and brightness. One method to increase the efficiency is to use the transparent oxides for the channel, electrode, and gate insulator. The development of transparent oxides for the components of thin-film field-effect transistors and the room-temperature fabrication with low voltage operations of the devices can offer the flexibility in designing the devices and contribute to the progress of next generation display technologies based on transparent displays and flexible displays. In this thesis, I report on the dc performance of transparent thin-film transistors using amorphous indium tin zinc oxides for an active layer. $SiO_2$ was employed as the gate dielectric oxide. The amorphous indium tin zinc oxides were deposited by RF magnetron sputtering. The carrier concentration of amorphous indium tin zinc oxides was controlled by oxygen pressure in the sputtering ambient. Devices are realized that display a threshold voltage of 4.17V and an on/off ration of ${\sim}10^9$ operated as an n-type enhancement mode with saturation mobility with $15.8\;cm^2/Vs$. In conclusion, the fabrication and characterization of thin-film transistors using amorphous indium tin zinc oxides for an active layer were reported. The devices were fabricated at room temperature by RF magnetron sputtering. The operation of the devices was an n-type enhancement mode with good saturation characteristics.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.2
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• pp.98-103
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• 2013

In this work, we investigated the enhanced performance of IZO-based TFTs with $HfSiO_x$ gate insulators. Four types of $HfSiO_x$ gate insulators using different diposition powers were deposited by co-sputtering $HfO_2$ and Si target. To simplify the processing sequences, all of the layers composing of TFTs were deposited by rf-magnetron sputtering method using patterned shadow-masks without any intentional heating of substrate and subsequent thermal annealing. The four different $HfSiO_x$ structural properties were investigated x-ray diffraction(XRD), atomic force microscopy(AFM) and also analyzed the electrical characteristics. There were some noticeable differences depending on the composition of the $HfO_2$ and Si combination. The TFT based on $HfSiO_x$ gate insulator with $HfO_2$(100W)-Si(100W) showed the best results with a field effect mobility of 2.0[$cm^2/V{\cdot}s$], a threshold voltage of -0.5[V], an on/off ratio of 5.89E+05 and RMS of 0.26[nm]. This show that the composition of the $HfO_2$ and Si is an important factor in an $HfSiO_x$ insulator. In addition, the effective bonding of $HfO_2$ and Si reduced the defects in the insulator bulk and also improved the interface quality between the channel and the gate insulator.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.5
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• pp.291-294
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• 2015

Recently, ZnO based oxide TFTs used in the flexible and transparent display devices are widely studied. To apply to OLED display switching devices, electrical performance and stability are important issues. In this study, to improve these electrical properties, we fabricated TFTs having Al doped Zinc Oxide (AZO) layer inserted between the gate insulator and ZnO layer. The AZO and ZnO layers are deposited by Atomic layer deposition (ALD) method. I-V transfer characteristics and stability of the suggested devices are investigated under the positive gate bias condition while the channel defects are also analyzed by the photoluminescence spectrum. The TFTs with AZO layer show lower threshold voltage ($V_{th}$) and superior sub-threshold slop. In the case of $V_{th}$ shift after positive gate bias stress, the stability is also better than that of ZnO channel TFTs. This improvement is thought to be caused by the reduced defect density in AZO/ZnO stack devices, which can be confirmed by the photoluminescence spectrum analysis results where the defect related deep level emission of AZO is lower than that of ZnO layer.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.11
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• pp.900-904
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• 2011

In this paper, we investigated an anomalous hump phenomenon under the positive bias stress in p-type LTPS TFTs. The devices with inferior electrical performance also show larger hump phenomenon. which can be explained by the sub-channel induced from trapped electrons under thinner gate oxide region. We can confirm that the devices with larger hump have larger interface trap density ($D_{it}$) and grain boundary trap density ($N_{trap}$) extracted by low-high frequency capacitance method and Levinson-Proano method, respectively. From the C-V with I-V transfer characteristics, the trapped electrons causing hump seem to be generated particularly from the S/D and gate overlapped region. Based on these analysis, the major cause of an anomalous hump phenomenon under the positive bias stress in p-type poly-Si TFTs is explained by the GIDL occurring in the S/D and gate overlapped region and the traps existing in the channel edge region where the gate oxide becomes thinner, which can be inferred by the fact that the magnitude of the hump is dependent on the average trap densities.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.479-479
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• 2011

Flexible inverters based on complementary thin-film transistor (CTFTs) are important because they have low power consumption and other advantages over single type TFT inverters. In addition, integrated CTFTs in flexible electronic circuits on low-cost, large area and mechanically flexible substrates have potentials in various applications such as radio-frequency identification tags (RFIDs), sensors, and backplanes for flexible displays. In this work, we introduce flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The CTFTs were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. Basic electrical characteristics of individual transistors and the whole CTFTs were measured by a semiconductor parameter analyzer (HP4145B, Agilent Technologies) at room temperature in the dark. Performance of those devices then was measured under static and dynamic mechanical deformation. Effects of cyclic bending were also examined. The voltage transfer characteristics (Vout- Vin) and voltage gain (-dVout/dVin) of flexible inverter circuit were analyzed and the effects of mechanical bending will be discussed in detail.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.910-912
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• 2009

투명전극은 비저항이 $1{\times}10^{-3}{\Omega}/cm$이하, 면저항이 $10^3{\Omega}/sq$이하로 전기전도성이 우수하고 380에서 780nm의 가시광선 영역에서의 투과율이 80%이상이라는 두 가지 성질을 만족시키는 박막이다. 기존의 평판디스플레이의 경우, 금속 산화물 투명전극이 진공 증착 공정을 통해 도포된 유리기판상의 각 화소를 포토리소그래피 공정으로 제조된 박막트랜지스터(TFT : Thin Film Transistor)로 제어함으로써 화상을 구현한다. 본 연구에서는 스퍼터링 진공 증착 장치를 이용하여 투명 도전막(ITO: Indium Tin Oxide)을 제작하고 제작된 ITO 박막의 광 및 전기 그리고 물성적 특성을 조사하여 최상의 공정 조건을 확립하였다. a-Si:H 박막위에 형성되는 ITo 박막은 a-Si:H 박막의 특성상 온도 및 스퍼터링 전력에 대한 연구가 주요 문제이다. 본 실험에서는 $In_2O_3:SnO_2$의 조성비는 90:10 wt% 인 타겟의 특성이 우수하였고, $Ar:O_2$의 분압비는 100:1 및 42:8 의 조건이 적당하였으며, 온도는 $200^{\circ}C$ 가장 우수한 특성을 얻을 수 있었다. $200^{\circ}C$ 는 비정질 실리콘의 성능에 좋은 영향을 미치는 온도이며, 알려진 것과 같이 $23^{\circ}C$ 즉 실온의 경우에 비해 막의 균질성 및 특성이 우수 한 것을 알 수 있었다. 본 연구에서 제작한 박막은 광 투과도가 90% 이상, 비저항이 $300{\mu}{\Omega}cm$ 이하의 특성을 갖게되어 이미지센서, 태양전지, 액정 텔레비젼등 빛의 통과와 전도성등 두가지 특성에 동시에 만족 될만한 성능을 가질 수 있음을 확인하였다.

• Journal of the Semiconductor & Display Technology
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• v.20 no.4
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• pp.157-160
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• 2021

As an insulator for a thin film transistor(TFT) and an encapsulation material of organic light emitting diode(OLED), aluminum oxide (Al₂O₃) has been widely studied using several technologies. Especially, in spite of low deposition rate, atomic layer deposition (ALD) has been used as a process method of Al₂O₃ because of its low process temperature and self-limiting reaction. In the Al₂O₃ deposition by ALD method, Ar Purge had some crucial effects on the film properties. After reaction gas is injected as a formation of pulse, an inert argon(Ar) purge gas is injected for gas desorption. Therefore, the process parameter of Ar purge gas has an influence on the ALD deposited film quality. In this study, Al₂O₃ was deposited on glass substrate at a different Ar purge time and its structural characteristics were investigated and analyzed. From the results, the growth rate of Al₂O₃ was decreased as the Ar purge time increases. The surface roughness was also reduced with increasing Ar purge time. In order to obtain the high quality Al₂O₃ film, it was known that Ar purge times longer than 15 sec was necessary resulting in the self-limiting reaction.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.344-344
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• 2014

Transparent amorphous oxide semiconductors such as a In-Ga-Zn-O (a-IGZO) have advantages for large area electronic devices; e.g., uniform deposition at a large area, optical transparency, a smooth surface, and large electron mobility >10 cm2/Vs, which is more than an order of magnitude larger than that of hydrogen amorphous silicon (a-Si;H).1) Thin film transistors (TFTs) that employ amorphous oxide semiconductors such as ZnO, In-Ga-Zn-O, or Hf-In-Zn-O (HIZO) are currently subject of intensive study owing to their high potential for application in flat panel displays. The device fabrication process involves a series of thin film deposition and photolithographic patterning steps. In order to minimize contamination, the substrates usually undergo a cleaning procedure using deionized water, before and after the growth of thin films by sputtering methods. The devices structure were fabricated top-contact gate TFTs using the a-IGZO films on the plastic substrates. The channel width and length were 80 and 20 um, respectively. The source and drain electrode regions were defined by photolithography and wet etching process. The electrodes consisting of Ti(15 nm)/Al(120 nm)/Ti(15nm) trilayers were deposited by direct current sputtering. The 30 nm thickness active IGZO layer deposited by rf magnetron sputtering at room temperature. The deposition condition is as follows: a rf power 200 W, a pressure of 5 mtorr, 10% of oxygen [O2/(O2+Ar)=0.1], and room temperature. A 9-nm-thick Al2O3 layer was formed as a first, third gate insulator by ALD deposition. A 290-nm-thick SS6908 organic dielectrics formed as second gate insulator by spin-coating. The schematic structure of the IGZO TFT is top gate contact geometry device structure for typical TFTs fabricated in this study. Drain current (IDS) versus drain-source voltage (VDS) output characteristics curve of a IGZO TFTs fabricated using the 3-layer gate insulator on a plastic substrate and log(IDS)-gate voltage (VG) characteristics for typical IGZO TFTs. The TFTs device has a channel width (W) of $80{\mu}m$ and a channel length (L) of $20{\mu}m$. The IDS-VDS curves showed well-defined transistor characteristics with saturation effects at VG>-10 V and VDS>-20 V for the inkjet printing IGZO device. The carrier charge mobility was determined to be 15.18 cm^2 V-1s-1 with FET threshold voltage of -3 V and on/off current ratio 10^9.

• Journal of Information Display
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• v.6 no.2
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• pp.16-18
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• 2005

Hybrid insulator pentacene thin film transistors (TFTs) are fabricated with thermally grown oxide and cross-linked polyvinylalcohol (PVA) including surface treatment by dilute ploymethylmethacrylate (PMMA) layer on $n^+$ doped silicon wafer. Through the optimization of $SiO_2$ layer thickness in hybrid insulator structure, carrier mobility is increased to more than 35 times than that of the TFT which has only a gate insulator of $SiO_2$ at the same electric field. The carrier mobility of $1.80cm^2$/V-s, subthreshold swing of 1.81 V/decade, and $I_{on}/I_{off}$ current ratio> $1.10{\times}10^5$ are obtained less than -30 V bias condition. The result is one of the best reported performances of pentacene TFTs with hybrid insulator including cross-linked PVA layer as a gate insulator at relatively low voltage operation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.3
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• pp.153-161
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• 2011

In this work, we report the physics-based SPICE model of amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) and demonstrate the SPICE simulation of amorphous InGaZnO (a-IGZO) TFT inverter by using Verilog-A. As key physical parameter, subgap density-of-states (DOS) is extracted and used for calculating the electric potential, carrier density, and mobility along the depth direction of active thin-film. It is confirmed that the proposed DOS-based SPICE model can successfully reproduce the voltage transfer characteristic of a-IGZO inverter as well as the measured I-V characteristics of a-IGZO TFTs within the average error of 6% at $V_{DD}$=20 V.