• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.87.5-87
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• 2001

In the past, we presented the tracking system with one sampling delay. In this paper, first we propose a tracking system with N-th sampling delay, in the case where an input-output pulse transfer function of a plant Z$\_$-N/. Secondly we propose a system configuration converting an input-output pulse transfer function of a plant into Z$\_$-N/ with the inverse system of the plant. Moreover, the proposed tracking system configuration is applied to an actual Ball and Beam system and good results are obtained.

• Journal of electromagnetic engineering and science
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• v.18 no.1
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• pp.20-28
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• 2018

The time synchronization of each sub-unit of a pulsed generator is important to generate an output high-power radio frequency (RF) signal. To obtain the time synchronization between an input RF signal fed by an external source and an electron beam produced by an electric pulse generator, the influence of different charging voltages on a delay and a rise time of the output pulse waveform in the electric pulse generator should be carefully considered. This paper aims to study the timing characteristics of the delay and the rise time as a function of different charging voltages with a peak value of less than -35 kV in the high-voltage pulse generator, including a trigger generator (TG) and a pulse-forming line (PFL). The simulation has been carried out to estimate characteristics in the time domain, in addition to their output high-voltage amplitude. Experimental results compared with those obtained by simulation indicate that the delay of the output pulses of the TG and PFL, which are made by controlling the external triggering signal with respect to different charging voltages, is getting longer as the charging voltage is increasing, and their rise times are inversely proportional to the amplitude of the charging voltage.

• Journal of Institute of Control, Robotics and Systems
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• v.18 no.7
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• pp.613-616
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• 2012

This paper proposes the state observer design for nonlinear systems with delayed output. It is shown that by considering a nonlinear term of error dynamics as an additional state variable, the nonlinear error dynamics with time delay can be transformed into the linear one with time delay. Sufficient conditions for existence of a state observer are characterized by linear matrix inequalities. Finally, an illustrative example is given in order to show the effectiveness of our design method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.259-262
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• 2012

This paper describes a delay-locked loop (DLL) that generates a 64-phase clock with the operating frequency of 125MHz. The proposed DLL use a $4{\times}8$ matrix-based delay line to improve the linearity of a delay line. The output clock with 64-phase is generated by using a CMOS multiplex and a inverted-based interpolator from 32-phase clock which is the output clock of the $4{\times}8$ matrix-based delay line. The circuit for an initial phase lock, which is independent on the duty cycle ratio of the input clock, is used to prevent from the harmonic lock of a DLL. The proposed DLL is designed using a $0.18-{\mu}m$ CMOS process with a 1.8 V supply. The simulated operating frequency range is 40 MHz to 200 MHz. At the operating frequency of a 125 MHz, the worst phase error and jitter of a 64-phase clock are +11/-12 ps and 6.58 ps, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.63-70
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• 2014

A low-N phase-locked loop clock generator with frequency multiplier is proposed to improve phase noise characteristic. Delay-variance voltage converter (DVVC) generates output voltages according to the delay variance of delay stages in voltage controlled oscillator. The output voltages of average circuit with the output voltages of DVVC are applied to the delay stages in VCO to reduce jitter. The HSPICE simulation of the proposed phase-locked loop clock generator with a $0.18{\mu}m$ CMOS process shows an 11.3 ps of peak-to-peak jitter.

• Journal of Power Electronics
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• v.12 no.1
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• pp.98-103
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• 2012

This paper presents a digital pulse width modulator (DPWM) with a reduced digital modulation delay (a transport delay of the modulator) during the transient response of power converters. During the transient response operation of a power converter, as a result of dynamic variations such as load step-up or step-down, the closed loop controller will continuously adjust the duty cycle in order to regulate the output voltage. The larger the modulation delays, the larger the undesired output voltage deviation from the reference point. The three conventional DPWM techniques exhibit significant leading-edge and/or trailing-edge modulation delays. The DPWM technique proposed in this paper, which results in modulation delay reductions, is discussed, experimentally tested and compared with conventional modulation techniques.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.34 no.2
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• pp.63-71
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• 1985

The existing methods of pole assignment were reserved in this paper, a digital control method for MIMO dynamic systems was developed based on pole assignment using I/O delay. The underlined concept of the derived control law was that the poles corresponding to the order of a system can be assigned on the desired positions via output delay, and the poles of the order incrememted by output delay were forced to be placed on zero positions by way of input delay when applied to an actual MIMO system, the present scheme was shown to be more effective than the conventional state feedback scheme with observer in that the former was simpler than the latter, while they performed well.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.7
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• pp.1158-1168
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• 1994

A variable structure control scheme(VSCS) with sliding mode that can be applied to the process with input/output(I/O) delay is proposed and its control performances is evaluated. The proposed VSCS with and output feedback scheme comprises a variable structure controller, a servo dynamic for tracking the set-poing, and a Smith predictor for compensating the effects of time delay. The robustness against the parameter variations and external disturbances can be achieved by the proposed VSCS even when the controlled process includes I/O delay. And the desired transient response is obtained by simple adjustment of the coefficients of the switching surface equation.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.379-381
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• 2004

In this paper, a robust $H_{\infty}$ stabilization problem to a uncertain fuzzy systems with time-varying delay via static output feedback is investigated. The Takagi-Sugeno (T-S) fuzzy model is employed to represent an uncertain nonlinear systems with time-varying delayed state. Using a single Lyapunov function, the globally asymptotic stability and disturbance attenuation of the closed-loop fuzzy control system are discussed. Sufficient conditions for the existence of robust $H_{\infty}$ controllers are given in terms of linear matrix inequalities.

• Journal of the Korean Society for Aviation and Aeronautics
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• v.18 no.4
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• pp.16-20
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• 2010

The dynamic characteristics of flight sensors is obtained by a simple method that deploys a pendulum with a rotary encoder. The encoder output is used with kinematic relations to derive reference signals for various flight sensors, including position, velocity, attitude, and angular rate sensors as well as accelerometer and magnetic sensors. A time delay of 0.4 seconds is found in the position output of the flight sensor under investigation. A logic to compensate for the time delay using a velocity information is proposed and validated in flight tests.