• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.819-825
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• 2016

In this paper, a phase locked loop structure with parallel dual loop which have a different bandwidth has been proposed. The bandwidths depending on transfer functions are obtained through dual loops. Two different bandwidths of each loop are used to suppress noise on the operating frequency range. The proposed phase locked loop has two different voltage controlled oscillator gains to control two different wide and narrow loop filters. Furthermore, it has the locking status indicator to achieve an accurate locking condition. The phase margin of $58.2^{\circ}$ for wide loop and $49.4^{\circ}$ for narrow loop is designed for stable operation and the phase margin of $45^{\circ}$ is maintained during both loops work together. It has been designed with a 1.8V 0.18um complementary metal oxide semiconductor (CMOS) process. The simulation results show that the proposed phase locked loop works stably and generates a target frequency.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.2
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• pp.95-104
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• 2011

In this paper, the metamaterial transmission line (TL) based on the complementary spiral resonators (CSRs) and interdigital structure is presented for reducing the phase noise of the voltage-controlled oscillator (VCO). The metamaterial TL is realized by adopting the array of the CSRs etched on the ground plane and the interdigital transmission line on the signal plane. The interdigital TL on the signal plane has been used to obtain higher Q value than the conventional TL without the interdigital structure. The resonance properties and inherent saturation of Q value of the proposed metamaterial TL have been analyzed by varying the width of the TL on the signal plane, dimensions of the CSRs, current directions between the CSRs, number of the unit cell-pair of the CSRs, and whether or not there is the interdigital structure in this paper. The phase noise and tuning range of the proposed VCO are -127.50~-125.33 dBc/Hz at 100 kHz and 5.744~5.852 GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.8
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• pp.964-969
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• 2007

A regulated low phase noise differential colpitts VCO(Voltage Controlled Oscillator) for mobile RFID system is presented. The differential colpitts VCO meets the dense reader environment specifications. The VCO use a $0.35{\mu}m$ technology and achieves tuning range $1.55{sim}2.053 GHz$. Measuring 910 MHz frequency divider output, phase noise performance is -106 dBcMz and -135dBc/Hz at 40 kHz and 1MHz offset, respectively. 5-bit digital coarse-tuning and accumulation type MOS varactors allow for 28.2% tuning range, which is required to cover the LO frequency range of a UHF Mobile RFID system, Optimum design techniques ensure low VCO gain(<45 MHz/V) for good interoperability with the frequency synthesizer. To the author' knowledge, this differential colpitts VCO achieves a figure of merit(FOM) of 1.93dB at 2-GHz band.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.1
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• pp.84-90
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• 2010

In this paper, a novel voltage-controlled oscillator (VCO) using the harmonic control circuit based on the composite right/left-handed (CRLH) transmission lines (TLs) is presented to reduce the phase noise without the reduction of the frequency tuning range and miniaturize the circuit size. The phase noise is reduced by the novel harmonic control circuit having the short impedances for the second- and third-harmonic components. The proposed harmonic control circuit is designed by using the CRLH TLs with the dual-band characteristic by the frequency offset and phase slope of the CRLH TLs. The high-Q resonator has been used to reduce the phase noise, but has the problem of the frequency tuning range reduction. However, the frequency tuning range of the proposed VCO has not been reduced because the phase noise has been reduced without the high-Q resonator. The miniaturization of the circuit size is achieved by using the CRLH TLs instead of the conventional right-handed (RH) TLs. The phase noise of VCO is -119.17 ~ -117.50 dBc/Hz at 100 kHz in the tuning range of 5.731 ~ 5.938 GHz.

• Journal of Korea Multimedia Society
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• v.14 no.5
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• pp.614-621
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• 2011

This paper presents design of a wide tuning range digitally controlled oscillator(DCO) for Mobile-DTV applications. DCO is the key element of the ADPLL block that generates oscillation frequencies. We proposed a binary delay chain(BDC) structure, for wide tuning range DCO, modifying conventional fixed delay chain. The proposed structure generates oscillation frequencies by delay cell combination which has a variable delay time of $2^i$ in the range of $0{\leq}i{\leq}n-1$. The BOC structure can reduce the number of delay cells because it make possible to select delay cell and resolution. We simulated the proposed DCO by Cadence's Spectre RF tool in 1.8V chartered $0.18{\mu}m$ CMOS process. The simulation results showed 77MHz~2.07GHz frequency range and 3ps resolution. The phase noise yields -101dBc/Hz@1MHz at Mobile-DTV maximum frequency 1675MHz and the power consumption is 5.87mW. The proposed DCO satisfies Mobile-DTV standards such as ATSC-M/H, DVB-H, ISDB-T, T-DMB.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.1
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• pp.23-28
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• 2016

In this paper, a Multi-Band Ku-band down converter was designed for reception of multi-band digital satellite broadcasting. The Multi-band low-nose down converter was designed to form four local oscillator frequencies (9.75, 10, 10.75 and 11.3GHz) representing a low phase noise due to VCO-PLL with respect to input signals of 10.7 to 12.75GHz and 3-stage low noise amplifier circuit by broadband noise matching, and to select an one band of intermediate frequency (IF) channels by digital control. The developed low-noise downconverter exhibited the full conversion gain of 64dB, and the noise figure of low-noise amplifier was 0.7dB, the P1dB of output signal 15dBm, and the phase noise -73dBc@100Hz at the band 1 carrier frequency of 9.75GHz. The low noise block downconverter (LNB) for receiving four-band digital satellite broadcasting designed in this paper can be used for satellite broadcasting of vessels navigating international waters.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.2
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• pp.115-122
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• 2016

In this paper, wideband Ku-band downconverter was designed to receiver digital satellite broadcasting. The low-nose downconverter was designed to form four local oscillator frequencies(9.75, 10, 10.75 and 11.3 GHz) representing a low phase noise due to VCO-PLL with respect to input signals of 10.7 to 12.75 GHz and 3-stage low noise amplifier circuit by broadband noise matching, and to select intermediate frequency bands by digital control. The developed low-noise downconverter exhibited the full conversion gain of 64 dB, and the noise figure of low-noise amplifier was 0.7 dB, the P1dB of output signal 15 dBm, and the phase noise -85 dBc@10kHz at the band 1 carrier frequency of 9.75 GHz. The low noise block downconverter(LNB) for wideband digital satellite broadcasting designed in this paper can be used for global satellite broadcasting LNB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.41-46
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• 2012

A quadrature voltage controlled oscillator(QVCO) for X-band is presented in this paper. The QVCO has fabricated in Charted $0.13{\mu}m$ CMOS process. The QVCO consists of two cross-coupled differential VCO and two differential buffers. The QVCO is controlled by 4 bit of capacitor bank and control voltage of varactor. To have a linear quality factor of varactors, voltage biases of varactors are difference. The QVCO generates frequency tuning range from 6.591 GHz to 8.012 GHz. The phase noise is -101.04 dBc/Hz at 1MHz Offset when output frequency is 7.150 GHz. The supply voltage is 1.5 V and core current 6.5-8.5 mA.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.5
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• pp.2357-2380
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• 2019

In this paper, we investigate the impact of hardware impairments (HWIs) on the performance of a downlink massive MIMO system. We consider a single-cell system with maximum ratio transmission (MRT) as precoding scheme, and with all the HWIs characteristics such as phase noise, distortion noise, and amplified thermal noise. Based on the system model, we derive closed-form expressions for a typical user data rate under two scenarios: when a common local oscillator (CLO) is used at the base station and when separated oscillators (SLOs) are used. We also derive closed-form expressions for the downlink transmit power required for some desired per-user data rate under each scenario. Compared to the conventional system with ideal transceiver hardware, our results show that impairments of hardware make a finite upper limit on the user's downlink channel capacity; and as the number of base station antennas grows large, it is only the hardware impairments at the users that mainly limit the capacity. Our results also show that SLOs configuration provides higher data rate than CLO at the price of higher power consumption. An approach to minimize the effect of the hardware impairments on the system performance is also proposed in the paper. In our approach, we show that by reducing the cell size, the effect of accumulated phase noise during channel estimation time is minimized and hence the user capacity is increased, and the downlink transmit power is decreased.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.13-22
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• 2010

This paper proposed the dual-loops multiphase DLL based mixed VCO/VCDL for a high frequency phase noise suppression of the input clock and the multiple frequencies generation with a precise duty cycle. In the proposed architecture, the dual-loops DLL uses the dual input differential buffer based nMOS source-coupled pairs at the input stage of the mixed VCO/VCDL. This can easily convert the input and output phase transfer of the conventional DLL with bypass pass filter characteristic to the input and output phase transfer of PLL with low pass filter characteristic for the high frequency input phase noise suppression. Also, the proposed DLL can correct the duty-cycle error of multiple frequencies by using only the duty-cycle correction circuits and the phase tracking loop without additional correction controlled loop. At the simulation result with $0.18{\mu}m$ CMOS technology, the output phase noise of the proposed DLL is improved under -13dB for 1GHz input clock with 800MHz input phase noise. Also, at 1GHz operating frequency with 40%~60% duty-cycle error, the duty-cycle error of the multiple frequencies is corrected under $50{\pm}1%$ at 2GHz the input clock.