• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.2A
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• pp.194-200
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• 2006

A 26.4 GHz phase locked oscillator(PLO) for communication satellite transponder is developed. The PLO consists of fundamental frequency generation module(FFGM) and frequency multiplication part(FMP). The signal of 26.4 GHz is generated through frequency tripling process of 8.8 GHz fundamental frequency. Phase locking technique using sampling phase detector(SPD) is adopted to design the FFGM. The MMIC tripler and amplifier are also designed for the reduction of the size and mass of FMP. The phase noise characteristics are exhibited as -96 dBc/Hz at 10 tHz offset frequency and -105 dBc/Hz at 100 kHz offset frequency, respectively, with the output power over 11 dBm. All performance parameters are complied with the design requirements.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.82-88
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• 2014

An available capacitance increasing phase-locked loop(PLL) with two voltage controlled oscillator gains has been proposed. In this paper, the available capacitance of loop filter is increased by using two positive/negative gains of voltage controlled oscillator (VCO). It results in 1/10 reduction in the size of loop filter capacitor. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the same phase noise characteristic and a locking time of conventional PLL.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.1
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• pp.17-24
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• 2008

This paper deals with a millimeter wave source which is utilizing sub-harmonic injection-synchronization technique. A 8.7GHz oscillator with MES-FET is fabricated, and is driven as a harmonic output oscillator at 17.4GHz by means of sub-harmonic injection-synchronization. The oscillator operates as a multiplier as well as oscillator in this system. Adopting this technique, we can obtain a high stable, high frequency millimeter wave source even though self-oscillating frequency of an oscillator is relatively low. In the experiments, the range of injection-synchronization is about 26MHz and is proportional to the input sub-harmonic power. From the spectrum analysis of the 2nd harmonic output. we blow that the phase noise of the harmonic oscillator is remarkably decreased.

• Journal of IKEEE
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• v.18 no.4
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• pp.625-629
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• 2014

This study derives the asymptotic phase noise formula of the oscillators perturbed by the colored noises. Based on the derived formula, this study presents a sub-1V series-tuned differential Colpitts VCO. The ADS simulation result on the phase noise shows that the presented VCO exhibits about 3dBc/Hz lower phase noise at the 1MHz offset frequency from the oscillation frequency of 4.8GHz than the existing series-tuned differential Colpitts VCO with the inductor current sources.

• Journal of IKEEE
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• v.15 no.1
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• pp.29-36
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• 2011

Dithering scheme has been widely used to improve the resolution of DCO(Digitally Controlled Oscillator) in conventional ADPLLs(All Digital Phase Locked Loop). In this paper a new resolution improvement scheme is proposed where a simple DAC is employed to overcome the problems of dithering scheme. A 2.4GHz LC-based DCO has been designed in a $0.13{\mu}m$ CMOS process with an enhanced frequency resolution for wireless local area network applications. It has a frequency tuning range of 900MHz and a resolution of 58.8Hz. The frequencies are controled by varactors in coarse, fine, and DAC bank. The DAC bank consists of an inversion mode NMOS varactor. The other varactor banks consist of PMOS varactors. Each varactor bank is controlled by 8bit digital signal. The designed DCO exhibits a phase noise of -123.8dBc/Hz at 1MHz frequency offset. The DCO core consumes 4.2mA from 1.2V supply.

• Journal of Advanced Navigation Technology
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• v.10 no.3
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• pp.235-249
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• 2006

In this paper, SER(Symbol Error Rate) variation and effects on SER by phase noise at various frequency offset of the local oscillator in digital communication systems are gerneralyzed for QPSK(Quadrature Phase Shift Keying), MQAM(M-ary Quadrature Amplitude Modulation), OFDM(Orthogonal Frequency Division Multiplex)-MQAM, OFDM-QPSK and 8-VSB(Vestigal Side Bands) modulation methods and compared those with the ideal cases, which have no phase noise, through the MATLAB simulation. And the ration between modulation bandwidths and the SER on the various frequency offsets on the above modulation methods have been analyzed for the system requirement of minimum phase noise characteristics. From this study, we have confirmed that the most sensitive modulation method on the phase noise is OFDM-MQAM and that the relatively insensitive method 8-VSB.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.1
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• pp.68-72
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• 2004

The integrated voltage-controlled-oscillator(VOC) operating at 1.75 ㎓ is designed using the InGaP/GaAs HBT process. The proposed noise removal circuit and FR-4 substrate structure in this letter show the better characteristic of the phase noise and reduce the size of the VCO. The frequency tuning range of the VCO is about 200 ㎒ and the phase noise at 120 ㎑ offset is -119.3 ㏈c/㎐. The power consumption of the VCO core is 11.2 ㎽ at 2.8 V supply voltage and the output power is -2 ㏈m. The calculated figure of merit(FOM) is 191.7, which shows the best performance compared with the previous FET or HBT VCO.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.4
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• pp.167-172
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• 2023

A low-noise phase-locked loop(PLL) with three negative feedback loops has been proposed. It is not easy to improve noise characteristics with a conventional PLL. The added negative feedback loops reduce the input voltage magnitude of voltage controlled oscillator which determines the jitter characteristics, enabling the improvement of noise characteristics. Simulation results show that the jitter characteristics are improved as a negative feedback loop is added. In the case of power consumption, it slightly rises by about 10%, but jitter characteristics are improved by about two times. The proposed PLL was simulated with Hspice using a 1.8V 180nm CMOS process.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.9
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• pp.1083-1089
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• 2007

In this paper, we applied the CMRC to a resonator to improve the harmonic characteristic of VCO. The CMRC filters have some advantage. It is a small size as well as easy to manufacture than PBG, DGS and other filters. This paper was proposed by using CMRC for a VCO. The second harmonic of -42.83 dBc and the phase noise at 100 kHz offset of -95.83 dBc/Hz was achieved, respectively. The VCO has better second harmonic character by 15.73 dB and phase noise by 31.13 dB in case of CMRC applied behind a resonator than CMRC used as a resonator.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.4
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• pp.598-603
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• 1990

This study evaluates the performance of an optical receiver for binary phase shift keying (BPSK) signals in the presence of short noise originating from the photo diode and phase noise of the optical source. The case of using I.O. hybrid compare with the fiber optic hybrid to mix received optical signal and laser local oscillator signal. The impact of these noise is minimized if loop natural frequency and power split ratio between data and carrier recovery branch are choosen optimally. Then it is obtained that required laser linewidt to achieve a BER of 10**-9. The results are the same except theat in case of using the fiber optic hybrid the required optical power is twice as much as the I.O. hybrid.