• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.1A
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• pp.104-112
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• 2005

Some design techniques for high speed and low power pipelined 8-bit ADC are described. To perform high-speed operation with relatively low power consumption, open loop architecture is adopted, while closed loop architecture (with MDAC) is used in conventional pipeline ADC. A distributed track and hold amplifier and a cascading structure are also adopted to increase the sampling rate. To reduce the power consumption and the die area, the number of amplifiers in each stage are optimized and reduced with proposed zero-crossing point generation method. At 500-MHz sampling rate, simulation results show that the power consumption is 210mW including digital logic with 1.8V power supply. And the targeted ADC achieves ENOB of about 8-bit with input frequency up to 200-MHz and input range of 1.2Vpp (Differential). The ADC is designed using a $0.18{\mu}m$ 6-Metal 1-Poly CMOS process and occupies an area of $900{\mu}m{\times}500{\mu}m$

• Transactions of the Korean Society of Machine Tool Engineers
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• v.10 no.1
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• pp.120-126
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• 2001

This study deals with a flow and pressure ripple characteristics for a hydrostatic transmission(HST) consisting of a vari-able axial piston pump connected in an open loop to a fixed displacement axial piston motor. These flow ripples produced by pump and motor in HST interacts with the source impedances of the pump or motor and dynamic characteristics of the connected pipeline, and results in a pressure ripples, Pressure ripples. Pressure ripples in HSP is major source of vibration, which can lead to fatigue failure of components and cause noise. In this paper, the flow ripples generated by a swash plate type axial piston pump or motor in HST are measured by making use of hydraulic pipeline dynamics and the measured pressure data at two points along the pipeline. By using the self-checking functions, the validity of the method us investigated by comparison with the measured and estimated pressure ripples at the halfway section of the pipeline, and good agreement is achieved.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.955-958
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• 2003

본 논문에서는 개방형 파이프라인 구조를 이용한 8비트 500Msamples/s ADC를 제안하였다. 8-비트의 해상도에 적합하면서 전력 소모가 적은 5 단 파이프라인 구조로 설계하였으며, 고속 동작에 적합하게 MUX 스위치에서 선택한 신호를 인터폴레이션하는 개방형 구조를 채택하였다. 전력 소모와 전체 칩 면적을 줄이기 위해서, 각 단에서 필요한 신호의 수를 줄이도록 설계하였다. 설계된 ADC 는 3 개의 신호를 이용하여 구현 함으로서 각 단에서의 증폭기 수틀 줄일 수 있었다. 또한 1.8V 의 낮은 전원 전압에 의한 작은 입력 범위에서 8-비트의 해상도를 만족하기 위해서 Offset Cancellation 기법을 사용하였다. 제안된 ADC 는 0.18μ m 일반 CMOS 공정을 이용하여 설계되었으며 시뮬레이션 결과 500Msamples/s에서 220mW의 전력 소모를 가지며, 1.2Vp-p (Differential) 입력 범위에 대해서 약 48dB의 SNDR을(8-비트의 해상도) 가짐을 확인할 수 있었다.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.11 no.3
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• pp.33-38
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• 2002

This paper deals with pressure ripple attenuation far separated-type Hydrostatic Transmission (HST) consisting ova variable axial piston pump connected in an open loop to a fried displacement axial piston motor. Pressure ripples in HST is major source of vibration which can lead to fatigue failure of components and cause noise. In order to reduce the pressure ripple, an annular tube tripe hydraulic filter is proposed to attenuate pressure ripples with the high frequencies components to achieve better noise reduction in HST. The basic principle of a hydraulic filter is allied to propagation of pressure wave, reflection, absorption in cross section of discontinuity and resonance in the hydraulic pipeline. It is experimentally shown that the hydraulic filter attenuates about 30∼40dB of pressure ripple with high frequencies. These results will assist in modeling and design of noise reduction in hydraulic control systems, and provide a means of designing a quieter HST.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2003.04a
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• pp.117-123
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• 2003

This paper deals with pressure ripple and noise reduction characteristics for a hydrostatic transmission(HST) consisting of a variable axial piston pump connected in an open loop to a fixed displacement axial piston motor. Pressure ripples in HST is major source of vibration, which can lead to fatigue failure of components and cause noise. In order to reduce the pressure ripple, an annular tube type hydraulic filter proposes to absorb pressure ripples with the high frequencies components to achieve better noise attenuation in HST. The basic principle tube is applied to propagation of pressure wave, reflection, absorption in cross section of discontinuity and resonance in the hydraulic pipeline. It is experimently confirmed that a hydraulic filter is absorbed to be about 30∼40dB of pressure ripple with high frequencies. These results will assist in modeling and design of noise reduction in hydraulic control systems, and here, should provide a means of designing a quieter HST.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.54-63
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• 2006

This work proposes a 14b 100MS/s 0.18um CMOS ADC with optimized resolution, conversion speed, die area, and power dissipation to obtain the performance required in the fourth-generation mobile communication systems. The 3-stage pipeline ADC, whose optimized architecture is analyzed and verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3-D fully symmetric layout techniques to minimize capacitor mismatch in two MDACs, and a back-end 6b flash ADC based on open-loop offset sampling and interpolation to obtain 6b accuracy and small chip area at 100MS/s. The prototype ADC implemented in a 0.18um CMOS process shows the measured DNL and INL of maximum 1.03LSB and 5.47LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 59dB and 72dB, respectively, and a power consumption of 145mW at 100MS/s and 1.8V. The occupied active die area is $3.4mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.53-60
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• 2005

This work proposes a 10b 100 MS/s $1.4\;mm^2$ CMOS ADC for low-power multimedia applications. The proposed two-step pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The wide-band SHA employs a gate-bootstrapping circuit to handle both single-ended and differential inputs with 1.2 Vp-p at 10b accuracy while the second-stage flash ADC employs open-loop offset sampling techniques to achieve 6b resolution. A 3-D fully symmetrical layout reduces the capacitor and device mismatch of the first-stage MDAC. The low-noise references are integrated on chip with optional off-chip voltage references. The prototype 10b ADC implemented in a 0.18 um CMOS shows the maximum measured DNL and INL of 0.59 LSB and 0.77 LSB, respectively. The ADC demonstrates the SNDR of 54 dB, the SFDR of 62 dB, and the power dissipation of 56 mW at 100 MS/s.