• 한국전기전자재료학회논문지
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• 제16권4호
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• pp.330-335
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• 2003

This paper reports the optimum structure of the vacuum packaged Porous poly-silicon Nano-Structured (PNS) emitter. The PNS layer was obtained by electrochemical etching process into polycrystalline silicon layer in a process controlled to anodizing condition. Current-voltage studies were carried out to optimize process condition of electron emission properties as a function of anodizing condition and top electrode thickness. Also, we measured in advance the electron emission properties as a function of substrate temperature because the vacuum packaged process was performed under the condition of high temperature ambient (430$^{\circ}C$). Auger Electron Spectrometer (AES) studies shows that Au as a top-electrode was diffused to PNS layer during temperature experiments. Thus, we optimized the thickness of top-electrode in order to make the vacuum package PNS emitter. As a result, the vacuum Packaged PNS emitter was successfully emitted by optimizing process.

• Applied Microscopy
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• 제45권2호
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• pp.89-94
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• 2015

This article briefly reviews the results of recently reported research on high-temperature Pb-free solder alloys and the research trend for characterization of the interfacial reaction layer. To improve the product reliability of high-temperature Pb-free solder alloys, thorough research is necessary not only to enhance the alloy properties but also to characterize and understand the interfacial reaction occurring during and after the bonding process. Transmission electron microscopy analysis is expected to play an important role in the development of high-temperature solders by providing accurate and reliable data with a high spatial resolution and facilitating understanding of the interfacial reaction at the solder joint.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권2호
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• pp.115-120
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• 2008

Carrier velocity in the MOSFET channel is the main driving force for improved transistor performance with scaling. We report measurements of the drift velocity of electrons and holes in silicon inversion layers. A technique for extracting effective carrier velocity which is a more accurate extraction method based on the actual inversion charge measurement is used. This method gives more accurate result over the whole range of $V_{ds}$, because it does not assume a linear approximation to obtain the inversion charge and it does not limit the range of applicable $V_{ds}$. For a very short channel length device, the electron velocity overshoot is observed at room temperature in 37 nm MOSFETs while no hole velocity overshoot is observed down to 36 nm. The electron velocity of short channel device was found to be strongly dependent on the longitudinal field.

• 반도체디스플레이기술학회지
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• 제5권3호
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• pp.23-27
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• 2006

Recently, Top emission organic light-emitting diode (TEOLED) has been attracted by their potential application for the development of flat panel display (FPD). We have fabricated the high luminance top emission organic-emitting diode (TEOLED) using dual cathode layer and three top emitting structure. These devices were characterized by electroluminescence (EL) and current density-voltage (J-V) measurements. After compared it with Au anode structure, luminance of the device using dual anode was better than using without Al device. Consequently, Al layers are very good candidates for a promising electron-injecting buffer layer for top emission light-emitting diode (TEOLED).

• 한국재료학회지
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• 제17권7호
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• pp.390-395
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• 2007

We systematically investigated the effects of InAs coverage variation, two-step annealing and an asymmetric InGaAs quantum well (QW) on the structural and optical characteristics of InAs quantum dots (QDs) by using atomic force microscopy (AFM), transmission electron microscopy (TEM) and photoluminescence (PL) measurement. The transition of size distribution of InAs QDs from bimodal to multi-modal was noticeably observed with increasing InAs coverage. By means of two-step annealing, it is found that significant narrowing of the luminescence linewidth (from 132 to 31 meV) from the InAs QDs occurs together with about 150 meV blueshift, compared to as-grown InAs QDs. Finally, the InAs QDs emitting at longer wavelength of $1.3\;{\mu}m$ with narrow linewidth were grown by an asymmetric InGaAs QW. The excited-state transition for the InAs QDs with an asymmetric InGaAs QW was not noticeably observed due to the large energy-level spacing between the ground states and the first excited states. The InAs QDs with an asymmetric InGaAs QW will be promising for the device applications such as $1.3\;{\mu}m$ optical-fiber communication.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권1호
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• pp.52-58
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• 2006

Single-electron transistor (SET)-based logic cells and SET/FET hybrid integrated circuits have been fabricated on SOI chips. The input-output voltage transfer characteristic of the SET-based complementary logic cell shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2K. The SET/FET output driver, consisting of one SET and three FETs, yields a high voltage gain of 13 and power amplification with a wide-range output window for driving next circuit. Finally, the SET/FET literal gate for a multi-valued logic cell, comprising of an SET, an FET and a constant-current load, displays a periodic voltage output of high/low level multiple switching with a swing as high as 200mV. The multiple switching functionality of all the fabricated logic circuits could be enhanced by utilizing a side gate incorporated to each SET component to enable the phase control of Coulomb oscillations, which is one of the unique characteristics of the SET-based logic circuits.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2012년도 춘계학술발표대회
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• pp.86.1-86.1
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• 2012

나노재료와 나노기술의 연구개발 지원을 위하여 국가나노인프라인 나노종합팹센터에서 개발되고 있는 나노재료/나노현상의 실시간 관찰을 위한 SiN membrane chip 기술 및 나노그래핀 기반구축에 대한 최근 결과와 향후계획을 소개하고자 한다. 나노재료의 합성, 배열, 구조 등의 실시간 관찰을 가능하게 하기 위하여 제작된SiN membrane chip은 투과전자현미경(transmission electron microscope, TEM)에서 투명한 기판으로, 그 위에 나노재료를 합성, 배열하고 원하는 모양의 전극을 형성하여 나노재료 및 나노소자의 온도변화 및 전기적 특성 측정 등이 가능하다. 이러한 기술은 Ag, Sn, Cu 등 nano-cluster의 percolation 소자, SiN 및 Graphene 나노기공 소자, SiGe, BiTe, Si, ZnO 나노선 및 CNT의 내부구조변화, 상변화 등 다양한 나노재료/나노소자의 나노현상 관찰 및 해석에 적용되었다.

• Applied Microscopy
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• 제36권spc1호
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• pp.35-40
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• 2006

Self-assembled InAs/GaAs quantum dots (QDs) were grown by the atomic layer epitaxy (ALE) and molecular beam epitaxy (MBE) techniques, The structure and the thermal stability of QDs have been studied by high resolution electron microscopy with in-situ heating experiment capability, The ALE and MBE QDs were found to form a hemispherical structure with side facets in the early stage of growth, Upon capping by GaAs layer, however, the apex of QDs changed to a flat one. The ALE QDs have larger size and more regular shape than those of MBE QDs. The QDs collapse due to elevated temperature was observed directly in atomic scale, In situ heating experiment within TEM revealed that the uncapped QDs remained stable up to $580^{\circ}C$, However, at temperature above $600^{\circ}C$, the QDs collapsed due to the diffusion and evaporation of In and As from the QDs, The density of the QDs decreased abruptly by this collapse and most of them disappeared at above $600^{\circ}C$.

• 한국전기전자재료학회논문지
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• 제18권12호
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• pp.1069-1074
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• 2005

In this work, nano-needle structures ate formed to solve problem, related to low density of quantum dots for nano floating gate memory. Such structures ate fabricated and electrical properties' of MIS devices fabricated on the nano-structures are studied. Nano floating gate memory based on quantum dot technologies Is a promising candidate for future non-volatile memory devices. Nano-structure is fabricated by reactive ion etching using $SF_6$ and $O_2$ gases in parallel RF plasma reactor. Surface morphology was investigated after etching using scanning electron microscopy Uniform and packed deep nano-needle structure is established under optimized condition. Photoluminescence and capacitance-voltage characteristics were measured in $Al/SiO_2/Si$ with nano-needle structure of silicon. we have demonstrated that the nano-needle structure can be applicable to non-volatile memory device with increased charge storage capacity over planar structures.

• 대한기계학회논문집A
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• 제32권6호
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• pp.459-464
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• 2008

We present a novel microcantilever device with nano-interdigitated electrodes (nano-IDEs) and DNA selective immobilization on the nano-IDEs for biosensing applications. Using the nano-IDEs and cyclic voltammetric methods, we have achieved selective immobilization of DNA with submicrometer spatial resolution on a freestanding microcantilever. $70{\sim}500\;nm$-wide gold (Au) nano-IDEs are fabricated on a low-stress SiNx microcantilever with dimensions of $100{\sim}600\;{\mu}m$ in length, and $15{\sim}60\;{\mu}m$ in width, with a $0.5\;{\mu}m$ thickness using electron beam lithography and bulk micromachining. Streptavidin is selectively deposited on one side of the nano-IDEs using cyclic voltammetry at a scan rate of 0.1 V/s with a range of $-0.2{\sim}0.7\;V$ during $1{\sim}5$ cycles. The selective deposition of dsDNA is confirmed by fluorescence microscopy after labeling with YOYO-1 dye.