• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1065-1068
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• 2003

For the first time, high quality ultra-thin strained Si/SiGe on Insulator (SGOI) substrate with total SGOI thickness( $T_{Si}$ + $T_{SiGe}$) of 13 nm is developed to combine the device benefits of strained silicon and SOI. In the case of 6- 10 nm-thick top silicon, 100-110 % $I_{d,sat}$ and electron mobility increase are shown in long channel nFET devices. However, 20-30% reduction of $I_{d,sat}$ and electron mobility are observed with 3 nm top silicon for the same long channel device. These results clearly show that the FETs operates with higher performance due to the strain enhancement from the insertion of SiGe layer between the top silicon layer and the buried oxide(BOX) layer. The performance degradation of the extremely thin( 3 nm ) top Si device can be attributed to the scattering of the majority carriers at the interfaces.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.46-52
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• 2012

Separate extraction of source ($R_S$) and drain ($R_D$) resistances caused by process, layout variations and long term degradation is very important in modeling and characterization of MOSFETs. In this work, we propose "Avalanche Hot-Source Method (AHSM)" for simple separated extraction of $R_S$ and $R_D$ in a single device. In AHSM, the high field region near the drain works as a new source for abundant carriers governing the current-voltage relationship in the MOSFET at high drain bias. We applied AHSM to n-channel MOSFETs as single-finger type with different channel width/length (W/L) combinations and verified its usefulness in the extraction of $R_S$ and $R_D$. We also confirmed that there is a negligible drift in the threshold voltage ($V_T$) and the subthreshold slope (SSW) even after application of the method to devices under practical conditions.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.11
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• pp.49-54
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• 1990

In this paper, a simple model is presented for the gate-voltage dependence of the parasitic resistance in MOSFETs with the lightly-doped drain (LDD) structure. At the LDD region located under the gate electrode, an accumulation layer is formed due to the gate voltage. The parasitic resistance of the source side LDD in the channel is treated as a parallel combination of the resistance of the accumulation layer and that of the bulk LDD, which is approximated as a spreading resistance from the end of the channel inversion layer to the ${n^+}$/LDD junction boundary. Also the effects of doping gradients at the junction are discussed. As result of the model, the LDD resistance decreases with increasing the gate voltage at the linear regime, and increase quasi-linearly with the gate voltage at the saturation regime, considering th velocity saturation both in the channel and in the LDD region. The results are in good agreement with experimental data reported by others.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.2
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• pp.36-45
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• 1993

The n-channel MOSFETs with gate-$n^{-}$S/D overlapped structure have been fabricated by ITLDD(inverse-T gate lightly doped drain) technology. The gate length(L$_{mask}$) was 0.8$\mu$m. The degradation effects of hot carriers injected into the gate oxide were analyzed in terms of threshold voltage, transconductance and drain current variations. The degradation dependences on the gate voltage and drain voltage were characterized. The devices with higher n-concentration showed higher resistivity against the hot carrier injection. As the results of investigating the lifetime of the device, the lifetime showed longer than 10 years at V$_{d}$ = 5V for the overlapped devices with the implantation of an phosphorus dose of 5$\times$10$^{13}$ cm$^{-2}$ and an energy of 80 keV in the n$^{-}$resion.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.8
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• pp.63-71
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• 1993

To verify validity of the steady-state Nyquist theorem and the steady-state Nyquist theorem with hot carrier effects in semiconductor devices, we calculate thermal noise in n-i-n structures using both the steady-state Nyquist theorem and the Monte-Carlo method, and compare the results from these two-methods. When the carrier temperature is not far from the lattice temperature, the results from both methods agree with each other very well, but in the hot carrier regime there are some discrepancies. Our results support the argument that for MOSFETs and MESFETs operating in the linear region, the channel thermal noise should be explained by the steady-state Nyquist theorem rather than by the existing theories.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.4
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• pp.271-275
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• 2011

In this paper, thermal stability of palladium germanide (Pd germanide) is analyzed for high performance Schottky barrier germanium metal oxide semiconductor field effect transistors (SB Ge-MOSFETs). Pd germanide Schottky barrier diodes were fabricated on n-type Ge-on-Si substrates and the formed Pd germanide shows thermal immunity up to $450^{\circ}C$. The barrier height of Pd germanide is also characterized using two methods. It is shown that Pd germanide contact has electron Schottky barrier height of 0.569~0.631 eV and work function of 4.699~4.761 eV, respectively. Pd germanide is promising for the nanoscale Schottky barrier Ge channel MOSFETs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2655-2661
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• 2009

In this paper, an accurate noise parameters for thermal noise modeling of short channel MOSFET is derived and extracted. Fukui model for calculating the noise parameters of a MOSFET is modified by considering effects of parasitic elements in short channel, and it is compared with conventional noise model equation. In addition, for obtaining the intrinsic noise sources of devices, noise parameters(minimum noise figure $F_{min}$, equivalent noise resistance $R_n$ optimized source admittance $Y_{opt}=G_{opt}+B_{opt}$) in submicron MOSFETs is extracted. With this extraction method, the intrinsic noise parameters of MOSFET without effects of probe pad and extrinsic parasitic elements from RF noise measurements can be directly obtained.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.133-133
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• 2008

Recently, as the down-scailing of field-effect transistor devices continues, Schottky-barrier field-effect transistors (SB-FETs) have attracted much attention as an alternative to conventional MOSFETs. SB-FETs have advantages over conventional devices, such as low parasitic source/drain resistance due to their metallic characteristics, low temperature processing for source/drain formation and physical scalability to the sub-10nm regime. The good scalability of SB-FETs is due to their metallic characteristics of source/drain, which leads to the low resistance and the atomically abrupt junctions at metal (silicide)-silicon interface. Nevertheless, some reports show that SB-FETs suffer from short channel effect (SCE) that would cause severe problems in the sub 20nm regime.[Ouyang et al. IEEE Trans. Electron Devices 53, 8, 1732 (2007)] Because source/drain barriers induce a depletion region, it is possible that the barriers are overlapped in short channel SB-FETs. In order to analyze the SCE of SB-FETs, we carried out systematic studies on the Schottky barrier overlapping in short channel SB-FETs using a SILVACO ATLAS numerical simulator. We have investigated the variation of surface channel band profiles depending on the doping, barrier height and the effective channel length using 2D simulation. Because the source/drain depletion regions start to be overlapped each other in the condition of the $L_{ch}$~80nm with $N_D{\sim}1\times10^{18}cm^{-3}$ and $\phi_{Bn}$ $\approx$ 0.6eV, the band profile varies as the decrease of effective channel length $L_{ch}$. With the $L_{ch}$~80nm as a starting point, the built-in potential of source/drain schottky contacts gradually decreases as the decrease of $L_{ch}$, then the conduction and valence band edges are consequently flattened at $L_{ch}$~5nm. These results may allow us to understand the performance related interdependent parameters in nanoscale SB-FETs such as channel length, the barrier height and channel doping.

• Journal of Information Display
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• v.8 no.4
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• pp.15-18
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• 2007

In this paper, we investigated the SLS process to control grain boundary(GB) location in TFT channel region, and it has been found to be applicable for locating the GB at the same location in the channel region of each TFT. We fabricated TFT by applying a new alignment SLS process and compared the TFT characteristics with a normal SLS method and the grain boundary location controlled SLS method. Also, we have analysed degradation phenomena under hot carrier stress conditions for n-type LDD MOSFETs.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.16-19
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• 2007

In this paper, we present work that has been carried out using the SLS process to control grain boundary(GB) location in TFT channel region and it is possible to locate the GB at the same location in the channel region of each TFT. We fabricated TFT by applying a new alignment SLS process and compared the TFT characteristics with a normal SLS method and the grain boundary location controlled SLS method. Also, we have analyzed degradation phenomena under hot carrier stress conditions for n-type LDD MOSFETs.