• Journal of Sensor Science and Technology
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• v.24 no.2
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• pp.79-82
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• 2015

This paper proposes a novel complementary metal oxide semiconductor (CMOS) active pixel sensor (APS) and presents its performance characteristics. The proposed APS exhibits a linear-logarithmic response, which is simulated using a standard $0.35-{\mu}m$ CMOS process. To maintain high sensitivity and improve the dynamic range (DR) of the proposed APS at low and high-intensity light, respectively, two additional nMOSFETs are integrated into the structure of the proposed APS, along with a photogate. The applied photogate voltage reduces the sensitivity of the proposed APS in the linear response regime. Thus, the conversion gain of the proposed APS changes from high to low owing to the addition of the capacitance of the photogate to that of the sensing node. Under high-intensity light, the integrated MOSFETs serve as voltage-light dependent active loads and are responsible for logarithmic compression. The DR of the proposed APS can be improved on the basis of the logarithmic response. Furthermore, the reference voltages enable the tuning of the sensitivity of the photodetector, as well as the DR of the APS.

• Journal of Electrical Engineering and information Science
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• v.3 no.3
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• pp.366-372
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• 1998

A high efficiency interleaved active clamp forward converter with self driven synchronous rectifiers for a modular power processor is presented. To simplify the gate drive circuits, N-P MOSFETs coupled active clamp method is used. An efficiency about 90% for the load range of 50-100% is achieved. The details of design for the power stage and current mode control circuit are provided, and also some experimental results are given.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2012.05a
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• pp.154-155
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• 2012

In this work, we report the comprehensive study of performance enhancement of InGaAs n-MOSFET by plasma $PH_3$ p assivation. The calibrated plasma $PH_3$ passivation of the InGaA ssurface before CVD high-k dielectric deposition significantly improves interface quality, resulting in suppressed frequency dispersion in C-V, increase in drive-current with high electron mobility, and excellent thermal stability.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.7
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• pp.464-472
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• 2001

Asymmetric n-MOSFET＇s for improving packing density have been fabricated with 0.35 ${\mu}{\textrm}{m}$ CMOS process. Electrical characteristics of asymmetric n-MOSFET show a lower saturation drain current and a higher linear resistance compared to those of symmetric devices. Substrate current of asymmetric MOSFET is lower than that of symmetric devices. Asymmetric n-MOSFET＇s have been modeled using a parasitic resistance associated with abnormally structured drain or source and a conventional n-MOSFET model. MEDICI simulation has been done for accuracy of this modeling. Simulated values of reverse as we11 as forward saturation drain current show good agreement with measured values for asymmetric device.

• Transactions on Electrical and Electronic Materials
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• v.12 no.2
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• pp.43-50
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• 2011

Carbon-nanotube metal oxide semiconductor field effect transistor (CN-MOSFET) is a promising future device candidate. The electrical characteristics of 16 nm N-type CN-MOSFETs are explored in this paper. The optimum N-type CN-MOSFET device profiles with different number of tubes are identified for achieving the highest on-state to off-state current ratio ($I_{on}/I_{off}$). The influence of substrate voltage on device performance is also investigated in this paper. Tradeoffs between subthreshold leakage current and overall switch quality are evaluated with different substrate bias voltages. Technology development guidelines for achieving high-speed, low-leakage, area efficient, and manufacturable carbon nanotube integrated circuits are provided.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1065-1068
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• 2003

For the first time, high quality ultra-thin strained Si/SiGe on Insulator (SGOI) substrate with total SGOI thickness( $T_{Si}$ + $T_{SiGe}$) of 13 nm is developed to combine the device benefits of strained silicon and SOI. In the case of 6- 10 nm-thick top silicon, 100-110 % $I_{d,sat}$ and electron mobility increase are shown in long channel nFET devices. However, 20-30% reduction of $I_{d,sat}$ and electron mobility are observed with 3 nm top silicon for the same long channel device. These results clearly show that the FETs operates with higher performance due to the strain enhancement from the insertion of SiGe layer between the top silicon layer and the buried oxide(BOX) layer. The performance degradation of the extremely thin( 3 nm ) top Si device can be attributed to the scattering of the majority carriers at the interfaces.

• Proceeding of EDISON Challenge
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• 2013.04a
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• pp.224-227
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• 2013

본 연구에서는 S/D이 n+/n+로 구성된 CNT-MOSFETs, 금속으로 이루어진 SB-CNTFETs와 p+/n+로 구성된 CNT-TFETs에 대한 각각의 $I_d-V_g$ 특성과 포텐셜 프로파일을 확인하였다. 그리고 각 소자의 특성 및 특징을 연구하고, 이 중에서 BTB에 가장 큰 영향을 받는 CNT-TFETs의 특성을 $V_{DS}$, 분자 비대칭성과 $T_{ox}$에 따른 특성 변화를 연구하였다. 그 결과 예상과 다르게 오히려 작은 $V_{DS}$와 큰 $E_g$을 가질 때, 향상된 SS를 가진다는 것을 확인 할 수 있었다. 특히, (7,0) CNT-TFETs에서 비록 $I_d$는 작지만, SS를 57mV/dec까지 개선할 수 있었다. 또한, $T_{ox}$를 얇게 하면, 비록 60 mV/dec 이하의 결과는 보여주지 못했지만, SS와 Ion 모두 개선할 수 있음을 확인할 수 있었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.24-29
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• 2009

In order to model the high temperature dependence of the cutoff frequency $f_T$ in $0.18{\mu}m$ deep n-well isolated bulk NMOSFET, high temperature data of electron velocity of bulk MOSFETs from $30^{\circ}C$ to $250^{\circ}C$ are obtained by an accurate RF extraction method using measured S-parameters. From these data, an improved temperature-dependent electron velocity equation is developed and implemented in a BSIM3v3 SPICE model to eliminate modeling error of a conventional one in the high temperature range. Better agreement with measured $f_T$ data from $30^{\circ}C$ to $250^{\circ}C$ are achieved by using the SPICE model with the improved equation rather than the conventional one, verifying its accuracy of the improved one.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.11
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• pp.49-54
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• 1990

In this paper, a simple model is presented for the gate-voltage dependence of the parasitic resistance in MOSFETs with the lightly-doped drain (LDD) structure. At the LDD region located under the gate electrode, an accumulation layer is formed due to the gate voltage. The parasitic resistance of the source side LDD in the channel is treated as a parallel combination of the resistance of the accumulation layer and that of the bulk LDD, which is approximated as a spreading resistance from the end of the channel inversion layer to the ${n^+}$/LDD junction boundary. Also the effects of doping gradients at the junction are discussed. As result of the model, the LDD resistance decreases with increasing the gate voltage at the linear regime, and increase quasi-linearly with the gate voltage at the saturation regime, considering th velocity saturation both in the channel and in the LDD region. The results are in good agreement with experimental data reported by others.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.3
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• pp.332-336
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• 2024

High-energy bandgap material silicon carbide (SiC) is gaining attention as a next-generation power semiconductor material, and in particular, SiC-based MOSFETs are developed as representative power semiconductors to increase the breakdown voltage (BV) of conventional planar structures. However, as the size of SJ (Super Junction) MOSFET devices decreases and the depth of pillars increases, it becomes challenging to uniformly form the doping concentration of pillars. Therefore, a structure with different doping concentrations segmented within the pillar is being researched. Using Silvaco TCAD simulation, a SJ VVD (vertical variation doping profile) MOSFET with three different doping concentrations in the pillar was studied. Simulations were conducted for the width of the pillar and the doping concentration of N-epi, revealing that as the width of the pillar increases, the depletion region widens, leading to an increase in on-specific resistance (R_on,sp) and breakdown voltage (BV). Additionally, as the doping concentration of N-epi increases, the number of carriers increases, and the depletion region narrows, resulting in a decrease in R_on,sp and BV. The optimized SJ VVD MOSFET exhibits a very high figure of merit (BFOM) of 13,400 KW/cm², indicating excellent performance characteristics and suggesting its potential as a next-generation highperformance power device suitable for practical applications.