• JSTS:Journal of Semiconductor Technology and Science
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• 제9권3호
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• pp.166-173
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• 2009

The reliability of hafnium oxide gate dielectrics incorporating lanthanum (La) is investigated. nMOSFETs with metal/La-doped high-k dielectric stack show lower $V_{th}$ and $I_{gate}$, which is attributed to the dipole formation at the high-k/$SiO_2$ interface. The reliability results well correlate with the dipole model. Due to lower trapping efficiency, the La-doping of the high-k gate stacks can provide better PBTI immunity, as well as lower charge trapping compared to the control HfSiO stacks. While the devices with La show better immunity to positive bias temperature instability (PBTI) under normal operating conditions, the threshold voltage shift (${\Delta}V_{th}$) at high field PBTI is significant. The results of a transconductance shift (${\Delta}G_m$) that traps are easily generated during high field stress because the La weakens atomic bonding in the interface layer.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2001년도 춘계종합학술대회
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• pp.317-320
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• 2001

본 논문에서는 Si-기반 나노채널 nMOSFET의 문턱전압에 관하여 분석하였다. 본 논문에서 연구된 소자는 180nm의 n-채널 MOSFET을 기준으로 30 nm까지의 게이트 길이를 가진 소사를 정전압 스켈링 이론에 따라 스켈링하였다. 이들 소자들은 드레인 영역에서의 전계크기 감소와 단채널 효과를 줄이기 위해 LDD(lightly doped drain) 구조를 사용하였으며 이들 소자의 문턱전압을 조사ㆍ분석하였다. 이러한 해석은 IC응용의 한계에 대한 분석을 제공할 것이며 VLSI의 기본 데이터로 활용될 수 있을 것이다.

• Advances in nano research
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• 제2권1호
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• pp.1-14
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• 2014

Dislocations are basic crystal defects and represent one-dimensional native nanostructures embedded in a perfect crystalline matrix. Their structure is predefined by crystal symmetry. Two-dimensional, self-organized arrays of such nanostructures are realized reproducibly using specific preparation conditions (semiconductor wafer direct bonding). This technique allows separating dislocations up to a few hundred nanometers which enables electrical measurements of only a few, or, in the ideal case, of an individual dislocation. Electrical properties of dislocations in silicon were measured using MOSFETs as test structures. It is shown that an increase of the drain current results for nMOSFETs which is caused by a high concentration of electrons on dislocations in p-type material. The number of electrons on a dislocation is estimated from device simulations. This leads to the conclusion that metallic-like conduction exists along dislocations in this material caused by a one-dimensional carrier confinement. On the other hand, measurements of pMOSFETs prepared in n-type silicon proved the dominant transport of holes along dislocations. The experimentally measured increase of the drain current, however, is here not only caused by an higher hole concentration on these defects but also by an increasing hole mobility along dislocations. All the data proved for the first time the ambipolar behavior of dislocations in silicon. Dislocations in p-type Si form efficient one-dimensional channels for electrons, while dislocations in n-type material cause one-dimensional channels for holes.

• 전자공학회논문지A
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• 제29A권11호
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• pp.91-96
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• 1992

The technology of LOCOS(LOCal Oxidation of Silicon) was used to form the island of SOI film. After this, the SOI film was recrystallized by CO$_2$ laser and metal gate nMOSFETs were fabricated on this SOI film and their electrical characteristics were measured. The kink effect was not nearly observed and edge channel effect was found in the SOI nMOSFETs. The threshold voltage was about 0.5V, the electron mobility was about 340cm$^2$V$\cdot$S and an ON/OFF ratio above 10$^{5}$ was obtained at V_{DS}$=4V. The electrical characteristics were improved by laser recrystallization.

• 대한전자공학회논문지SD
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• 제40권9호
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• pp.638-643
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• 2003

Channel width dependence of hot-carrier effect in nMOSFET with shallow trench isolation is analyzed. $I_{sub}$- $V_{G}$ and $\Delta$ $I_{ㅇ}$ measurement data show that MOSFETs with narrow channel-width are more susceptible to the hot-carrier degradation than MOSFETs with wide channel-width. By analysing $I_{sub}$/ $I_{D}$, linear $I_{D}$- $V_{G}$ characteristics, thicker oxide-thickness at the STI edge is identified as the reason for the channel-width dependent hot-carrier degradation. Using the charge-pumping method, $N_{it}$ generation due to the drain avalanche hot-carrier (DAHC) and channel hot-electron (CHE) stress are compared. are compared.

• Journal of Power Electronics
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• 제16권1호
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• pp.84-92
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• 2016

Compared with Si MOSFETs, the GaN FET has many advantages in a wide band gap, high saturation drift velocity, high critical breakdown field, etc. This paper compares the electrical properties of GaN FETs and Si MOSFETs. The soft-switching condition and power loss analysis in a flyback-forward high gain DC/DC converter with a GaN FET is presented in detail. In addition, a comparison between GaN diodes and Si diodes is made. Finally, a 200W GaN FET based flyback-forward high gain DC/DC converter is established, and experimental results verify that the GaN FET is superior to the Si MOSFET in terms of switching characteristics and efficiency. They also show that the GaN diode is better than the Si diode when it comes to reverse recovery characteristics.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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• pp.485-488
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• 1999

In this paper, the effects of back-gate bias on n-channel SOI MOSFETs has been systematically investigated. Back-gate surface is accumulated when negative bias is applied. It is found that the driving current ability of SOI MOSFETs is reduced because the threshold voltage and subthreshold slope are increased and transconductance is decreased due to the hole accumulation in Si body.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1990년도 추계학술대회 논문집
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• pp.55-59
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• 1990

N-Channel polysilicon MOSFETs (W/L=20/1.5, 3, 5.10$\mu\textrm{m}$) were fabricated using RTP(Rapid Thermal Processor) and hydrogen passivation. The N+ Source, drain and gate were annealed and recrystallized using RTP at temperature of 1000$^{\circ}C$-1100$^{\circ}C$. But the active areas were now specially crystallized before growing the gate oxide. Without the hydrogen passivation, excellent transistor characteristics (ON/OFF=5${\times}$10$\^$6/, s=85mv/dec, I$\_$L/=51pA/$\mu\textrm{m}$) were obtained for 1.5$\mu\textrm{m}$ MOSFET. Also the transistor characteristics were improved by hydrogen passivation.

• 대한전자공학회논문지SD
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• 제40권10호
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• pp.32-38
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• 2003

SIMOX 웨이퍼를 사용하여 제작된 GAA 구조 SOI MOSFET의 열전자에 의한 소자열화를 측정·분석하였다. nMOSFET의 열화는 스트레스 게이트 전압이 문턱전압과 같을 때 최대가 되었는데 이는 낮은 게이트 전압에서 PBT 작용의 활성화로 충격이온화가 많이 되었기 때문이다. 소자의 열화는 충격이혼화로 생성된 열전자와 홀에의한 계면상태 생성이 주된 원인임을 degradation rate와 dynamic transconductance 측정으로부터 확인하였다. 그리고 pMOSFET의 열화의 원인은 DAHC 현상에서 생성된 열전자 주입에 의한 전자 트랩핑이 주된 것임을 스트레스 게이트 전압변화에 따른 드레인 전류 변화로부터 확인 할 수 있었다.

• 전력전자학회논문지
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• 제10권3호
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• pp.274-281
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• 2005

압전소자를 에너지원으로 사용하여 자립형 전기전자시스템에 에너지를 공급하는 에너지 획득(Harvesting) 개념의 구현을 위하여, 새로운 AC/DC 공진형 펄스 컨버터를 제안한다. 컨버터는 정류기와 DC 컨버터의 2단계로 구성되었으며, AC/DC 변환을 위한 정류기는 MOSFET의 3상한 동작 특성을 이용하여 구현하고, N형 및 P형 MOSFETs을 사용하여 DC/DC 부스트 컨버터를 구현하였다. 제안된 컨버터 시스템의 동작원리 및 동작모드를 스위칭 소자의 기생캐패시턴스를 고려하여 해석하고, 시뮬레이션을 통하여 해석결과를 검증하였다. CMOS IC 칩으로 제작된 본 시스템의 실험 결과는 수십 uW 용량에서 에너지 획득 개념의 구현 가능성을 제시하였다.