• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.62-68
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• 2007

H.264 video compression in digital multimedia broadcasting (DMB) shows significantly high compression ratio over conventional algorithms, while its required hardware cost and power consumption are also $3{\sim}5$ times larger. Consequently, low-hardware-cost and low-power H.264 decoder SoC is essential for commercial digital multimedia broadcasting terminals. This paper describes low-power design and implementation of core blocks in H.264 decoder SoC.

• ETRI Journal
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• v.25 no.5
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• pp.297-304
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• 2003

A multimedia SoC often requires a large internal buffer, because it must store the whole search window to reduce the huge I/O bandwidth of motion estimation. However, the silicon area of the internal buffer increases tremendously as the search range becomes larger. This paper proposes a new method that greatly reduces the internal buffer size of a multimedia SoC while the computational cost, I/O bandwidth, and image quality do not change. In the proposed method, only the overlapped parts of search windows for consecutive macroblocks are stored in the internal buffer. The proposed method reduces the internal buffer. The proposed method reduces the internal buffer size to 1/5.0 and 1/8.8 when the search range is ${\pm}64{\times}{\pm}$64 and ${\pm}128{\times}{\pm}$128, respectively.

• Journal of Korea Multimedia Society
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• v.19 no.2
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• pp.122-127
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• 2016

This paper propose implementation method of SoC system for efficient depth image segmentation. SoC systems are combined platform in the form of the Software and Hardware IP. In order to perform effectively, the user to determine the operation of the configuration of each part. In this paper, we implemented a segmentation of depth images taken by the infrared sensor at APU of SoC system. The proposed method efficiently implements high performance and low power in SoC system. Proposed method that using software parts of SoC system is capable to use at several depth image processing systems.

• Journal of Korea Multimedia Society
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• v.12 no.5
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• pp.617-632
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• 2009

In this paper we propose a technique of implementing the reconfigurable network protocol stack that allows for partitioning network protocol functions into software and hardware tasks on a SoC (System on Chip) platform. Additionally, we present a method that guarantees the deadline of both an individual task and messages exchanging among tasks in order to meet the deadline of real-time multimedia and networking services. The proposed real-time message exchange method guarantees the deadline of messages generated by multimedia services that are required to meet the real-time properties of multimedia applications. After implementing the networking functions of TCP/IP protocol suite into hardware and software tasks, we verify and validate their performance on the SoC platform. Experimental results indicate that the proposed technique improves the performance of TCP/IP protocol suit as well as application service satisfaction in application-specific real-time.

• Journal of Korea Multimedia Society
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• v.17 no.3
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• pp.324-332
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• 2014

This paper presents a programmable System-On-a-chip for various embedded applications that need Neural Network computations. The system is fully implemented into Field-Programmable Gate Array (FPGA) based prototyping platform. The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using real image processing applications, such as optical character recognition (OCR) system.

• The Journal of the Korea Contents Association
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• v.7 no.11
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• pp.84-93
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• 2007

This paper presents a methodology that accelerates estimating the system-level power consumption for on-chip bus of SoC platforms. The proposed power modeling can estimate the power consumption according to the change of a target SoC system. The proposed model comprises two parts: the one is power estimation of bus logics reflecting the architecture of the bus such as the number of bus layers, the other is to estimate the power consumed by the bus lines during data transmission. We designed the target multimedia SoC system, MPEG encoder as an example and evaluated power consumption using this model. The simulation result shows that the accuracy of the proposed model is over 92%. Thus, the proposed power model can be used to design of a high-performance/low-power multimedia SoC.

• Korea Multimedia Society
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• v.16 no.1
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• pp.1-8
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• 2012

• Korea Multimedia Society
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• v.16 no.3
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• pp.1-7
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• 2012

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.397-400
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• 2009

This paper describes ASIC design of Multimedia application SoC platform based RISC processor with BTB(Branch Target Buffer). For performance enhancement of platform, we use a simple branch prediction scheme, BTB structure, that stores a target address for branch instruction to remove pipeline harzard. Also, the platform includes a number of peripheral such as VGA controller, AC97 controller, UART controller, SRAM interface and Debug interface. The platform is designed and verified on a Xilinx VERTEX-4 FPGA using a number of test programs for functional tests and timing constraints. Finally, the platform is implemented into a single ASIC chip which can be operated at 100MHz clock frequency using the Chartered 0.18um process. As a result of performance estimation, the proposed platform shows about 5~9% performance improvement in comparison with the previous SoC Platform.

• Smart Media Journal
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• v.1 no.1
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• pp.27-35
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• 2012

In this paper, the performance analysis for multimedia video codec(MPEG-4, H.264) on on-chip network communication architecture is presented. The On-Chip Network (OCN) is the new communication architecture of multimedia SoC design that overcomes the limits of On-Chip Bus architecture by providing higher data traffic bandwidth, reusability and higher scalability. We compared the performance of MPEG-4, H.264 decoder based on-chip network and AMBA on-chip bus. Experimental results show that the performance of MPEG-4, H.264 based on on-chip network is improved over 33~56% compared to the design based on AMBA on-chip bus.