• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.1C
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• pp.14-23
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• 2003

This thesis proposes a sigma-delta modulator architecture with 2 Ms/s data rate and 12 bit resolution. A sigma-delta modulate has the features of oversampling and noise shaping. With these features, it can be connected with low resolution A/D converter to achieve higher resolution A/D converter. Most previous researches have been concentrated on high resolution but low data rate applications, e.g. audio applications. But, in order to be applied to various applications such as wireless data communication, researches on sigma-delta modulator architecture for higher data rate are required. The proposed sigma-delta modulator architecture has the sampling rate of 16 times Nyquist rate to achieve high data rate, and consists of a cascade of two 2nd order sigma-delta modulator to get relatively high resolution. The experimental result shows that the proposed architecture achieves 12-bit resolution at 2 Ms/s data rate.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.446-450
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• 2011

Tunable SC(Switched Capacitor) bandpass ${\Sigma}-{\Delta}$(Sigma-Delta) modulator used in wireless system receiver occurs a signal attenuation according to tuning of center frequency in signal bandwidth. In this paper, tunable bandpass 4th order SC bandpass ${\Sigma}-{\Delta}$ modulator with novel structure is proposed for rejection of signal attenuation in signal bandwidth. The existing structure uses a ten variable coefficient values for rejection of signal reduction in the modulator. But the proposed structure only use a two variable coefficient values for rejection of signal attenuation in the modulator. Also, an adder and comparator is replaced with a comparator having 4 inputs in the modulator. Therefore, the existing structure has one more OP-AMP. The purposed modulator was designed in $0.18\;{\mu}m$ CMOS technology. The resolution of the modulator within 310 kHz bandwidth and 40 MHz sampling frequency under 6.67 MHz, 10 MHz and 13.33 MHz intermediate frequency are over 10 bit.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.290-292
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• 2007

A twisted nematic type liquid crystal electro-optic modulator (TN-LC modulator) was developed. The modulator used single polarizer and the reflection on-off ratio was maximized by optimization of twist angle and retardation of liquid crystal cell. The TNLC modulator shows better sensitivity and response time than conventional liquid crystal modulator.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.6
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• pp.1081-1086
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• 2008

This paper presents the $3^{rd}$ 4bit sigma delta modulator with the block and timing diagrams of DWA(Data Weighted Averaging) to optimize a operating time. In the modulator, the proposed DWA structure has a stable operation and timing margin so as to remove three latches and another clock. Because the modulator with proposed DWA structure improve timing margin about 23%. It can increase sampling frequency up to 244MHz. Through the MATLAB modeling, the optimized coefficients are obtained to design the modulator. The fully differential SC integrators, DAC, switch, quantizer, and DWA are designed by considering the nonideal characteristics. The designed $3^{rd}$ order 4bit modulator has a power consumption of 40mW and SNR(signal to noise ratio) of 77.2dB under 1.2V supply and 64MHz sampling frequency.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.136-141
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• 2016

A phase-locked loop(PLL) with effectively increased capacitance by current modulator has been proposed. In this paper, the effective capacitance of loop filter is increased by using current modulator and it results in 1/10 reduction of capacitance in loop filter. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the same phase noise characteristic and locking time of conventional PLL.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.9
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• pp.650-656
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• 2004

This paper presents block and timing diagrams of the DWA(data weighted averaging) to optimize a feedback time delay of the sigma-delta modulator. Through the Matlab modeling, the optimized coefficients of the integrators are obtained to design the modulator. And then the fully differential SC integrators, feedback DAC, 9-level quantizer, and DWA are designed by considering the nonideal characteristics of the modulator. The designed second-order multibit modulator is fabricated in a 0.35$\mu\textrm{m}$ CMOS process. The designed modulator achieves 73dB signal-to-noise ratio and 72dB dynamic range at 1.2Vp-p 585kHz input singal and 52.8MHz sampling frequency.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.05a
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• pp.54-57
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• 1992

An electro-optical single modulator is fabricated in X-cut LiNbO$_3$by the annealed proton exchange and self-aligned method. First, the effect of annealing is characterized by examining single optical modulator. It is found that by controlling the annealing time, the single optical modulator can be made widely variable. The on-off state of modulator is performed by annealing process and self-aligned electrodes are used in fabricating the single modulator. The optical single modulator has very good figures of merits : the measured on-off switching voltage of about 2.7V.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.307-308
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• 2019

The Pohang Light Source (PLS) - II is a 3 GeV third-generation synchrotron radiation facility. To inject electron beam from LINAC, a kicker modulator system and kicker magnets are installed in the PLS-II storage ring tunnel. The injected beam then falls into the storage ring beam dynamic aperture. This paper describes the design and implementation of the solid-state kicker modulator for PLS-II. The solid-state kicker modulator is consisted of high voltage solid state switch stacks. the technical considerations of the solid-state switch stacking for kicker modulator is discussed. The achieved capability of the solid-state kicker modulator demonstrates that is fulfills the design requirement of providing half-sine pulsed current of 10kA (peak), 6us (Base-width), with jitter < 2ns (Standard deviation). simulation and experimental results are presented to demonstrate the performance of the solid-state kicker modulator.

• 한국약용작물학회:학술대회논문집
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• 2011.04a
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• pp.94-95
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• 2011

• Proceedings of the Acoustical Society of Korea Conference
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• 1987.11a
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• pp.93-97
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• 1987

In this paper a SAW based AWZPSK modulator using the classical truncated cosine series functoins as a baseband pulse is described. A SAW AWQPSK modulator has been designed and fabricated on YZ-LINBO3 substrates. Measured responses meet the theoretical values with tolerable amounts of deviation. This SAW-based device shows good performance as a simple AWQPSK modulator.