• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.199-201
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• 2020

본 논문은 DC-DC 컨버터 스위칭 동작 시 입력 단에 영향을 미치는 차동 노이즈 분석을 위한 고주파 등가모델을 제안하였으며, DC-DC 벅 컨버터 프로토타입을 제작하고 실험을 통해 검증하였다. 고주파 등가모델에는 DC 부스바, IGBT 및 PCB 등에 포함되는 기생 임피던스 성분들을 모두 고려하였으며, DC-DC 컨버터의 온/오프 스위칭 동작에 따른 차동모드 노이즈 영향 분석을 위한 수학적 모델을 개발하였다. 실험구성은 벅 컨버터, 스펙트럼 분석기, 네트워크 분석기 및 LISN 장비로 구성하였으며, 150kHz ~ 30MHz의 주파수 범위 내에서 측정된 공진주파수가 제안된 고주파 등가 모델의 분석결과와 실험결과가 일치함을 도출함으로써 제안된 등가 모델의 타당성을 검증하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.11C
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• pp.1085-1097
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• 2009

We present a structure and design method of the D8PSK modem compatible with the VDL mode-2 standard and performance test results of the developed modem. In VDL mode-2, the raised cosine filter is used only in the transmitter and a general low pass filter is used in the receiver. Consequently, we can not achieve ISI reduction but can have better spectrum characteristics. Although there is 1~2 dB performance degradation with an un-matched filter compared to that with a matched filter, it is more important to minimize adjacent channel interference in narrow band communications. The transmit signal is generated digitally to avoid the problems(I/Q imbalance and DC offset etc.) of analog modulators. In addition the digital down converter using digital IF sampling technique is adopted for the receiver. This paper contains the overall configuration, design method and simulation results based in part on the previously proposed structures and algorithms. It is confirmed that the modem transmits and receives messages successfully at a speed of max. 870 km/h over ranges of up to 310 km through the ground and in-flight communication tests.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.2
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• pp.199-208
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• 2012

This paper proposes a quasi Z-source DVR(Dynamic Voltage Restorer) system with a series connection of the output terminals, to compensate the voltage variations in the 6.6[kV]/60[Hz] power distribution system. The conventional DVR using one quasi Z-source AC-AC converter has the advantage which it can compensate the voltage variations without the need for the additional energy storage device such as a battery, but it is impossible to compensate for the 50[%] under voltage sags. To solve this problem, a DVR system using two quasi Z-source AC-AC converters with the series connection of the output terminals is proposed. By controlling the duty ratio D in the buck-boost mode, the proposed system can control the compensation voltage. For case verification of the proposed system, PSIM simulation is achieved. As a result, in case that the voltage sags-swells occur 10[%], 20[%], 60[%] in power distribution system, and, in case that the 50[%] under voltage sags-swells continuously occur, all case could compensate by the proposed system. Especially, the compensated voltage THD was examined under the condition of the 10[%]~50[%] voltage sags and the 20[${\Omega}$]~100[${\Omega}$] load changes. The compensated voltage THD was worse for the higher load resistances and more severe voltage sags. Finally, In case of the voltage swells compensation, the compensation factor has approached nearly 1 regardless of the load resistance changes, while the compensation factor of voltage sags was related to the load variations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.11
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• pp.828-835
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• 2001

Novel bipolar transresistance amplifier(TRA) and its offset-compensated TRA for high-performance current-mode signal processing are described. The TRA consist of two current follower for a current inputs, a current summer for the current-difference, a resistor for the current to voltage converter, and a voltage follower for the voltage output. The offset-compensated TRA adopts diode-connected npn and pnp transistor to reduce offset voltage in the TRA. The simulation results show that the TRA has impedance of 0.5 Ω at the input and the output terminal. The offset voltages at these terminals is 40 mV The offset-compensated TRA has the offset voltage of 1.1 mV and the impedance of 0.25 Ω. The 3-dB cutoff frequency is 40 MHz for the two TRA＇s when used as a current to voltage converter with unit-gain transresistance. The power dissipation is 11.25 mW.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.7
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• pp.1543-1551
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• 2011

Dithering scheme has been widely used to improve the resolution of DCO(Digitally Controlled Oscillator) in conventional ADPLLs(All Digital Phase Locked Loop). In this paper a new resolution improvement scheme is proposed where a simple DAC(Digital-to-Analog Converter) is employed to overcome the problems of dithering scheme. The frequencies are controled by varactors in coarse, fine, and DAC bank. The DAC bank consists of an inversion mode NMOS varactor. The other varactor banks consist of PMOS varactors. Each varactor bank is controlled by 8bit digital signal. The proposed DCO has been designed in a $0.13{\mu}m$ CMOS process. Measurement results shows that the designed DCO oscillates in 2.8GHz~3.5GHz and has a frequency tuning range of 660MHz and a resolution of 73Hz at 2.8GHz band. The designed DCO exhibits a phase noise of -119dBc/Hz at lMHz frequency offset. The DCO core consumes 4.2mA from l.2V supply. The chip area is $1.3mm{\times}1.3mm$ including pads.

• Proceedings of the KIPE Conference
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• 2004.07a
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• pp.77-81
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• 2004

In this paper a novel line interactive UPS (Uninterruptible Power Supply) using the two 4-leg VSCs and AC line reactor is proposed. The 4-leg Voltage Source Converter(VSC) can use the DC link voltage effectively by the 3-D SVPWM method. Hence the DC battery voltage can be reduced by $15\%$ in comparison to that of the conventional line-interactive UPS system. One VSC is in parallel with the AC line reactor of the power source side, and the other is in series with the load. The parallel 4-leg voltage source inverter controls three-phase line voltage independently in order to control the line reactor current indirectly. It eliminates the neutral line current and the active ripple power of the source side using the pqr theory so that unity power factor and the sinusoidal source current can be achieved even though both the source and the load voltages have zero sequence components. The series 4-leg voltage source inverter compensates the line voltage and allows the load voltage to be balanced and harmonic-free. Both of parallel and series 4-leg voltage source inverters always act as independently controllable voltage sources, so that three-phase output voltage shows a seamless transition to the backup mode. The feasibility of the proposed UPS system has been investigated and verified through computer simulation results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.7
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• pp.623-629
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• 2013

This paper presents the implementation result of the EEG(electroencephalogram) signal transmission protocol and its test platform. EEG measured by a dry-type electrode is directly converted into digital signal by ADC(analog-to-digital converter). Thereafter it is transferred DSP(digital signal processor) platform by $I^2C$(inter-integrated circuit) protocol. DSP conducts the pre-processing of EEG and extracts feature vectors of EEG. In this work, we implement the $I^2C$ protocol with 16 channels by using 10 or 12-bit ADC. In the implementation results, the overhead ratio for the 4 bytes data burst transmission measures 2.16 and the total data rates are 345.6 kbps and 414.72 kbps with 10-bit and 12-bit 1 ksps ADC, respectively. Therefore, in order to support a high speed mode of $I^2C$ for 400 kbps, it is required to use 16:1 and $(8:1){\times}2$ ratios for slave:master in 10-bit ADC and 12-bit ADC, respectively.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.2
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• pp.151-155
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• 2016

In this paper, we present the LED dimming control system by using ADPCM (Adaptive Differential Pulse Code Modulation). This ADPCM apparatus accurately controls the LED current with high resolution reducing the RFI (radio frequency interference) due to the spreading out of the harmonics of current of pulses. Additionally, this makes it easier to increase the accuracy of control operation. This study introduces to make a digitally controlled circuit for controlling LED with high-energy efficient by adopting pulse current to LED. The LED current drive system we designed are two systems, the digitally-controlled unit and analog switching mode power supply unit, can be developed separately. The simulation shows the sigma delta modulation of digital to analog converter's output when the input level is 0.7. From this simulation, the output is approached to accurately 0.15% to target value with 510 pulses.

• Journal of Power Electronics
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• v.11 no.6
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• pp.870-879
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• 2011

Regulated peak power tracking (RPPT) systems such as the series structure and the series-parallel structures are commonly used in satellite space power systems. However, these structures process the solar array power or the battery power to the load through two cascaded regulators during one orbit cycle, which reduces the energy transfer efficiency. Also the battery charging time is increased due to placement of converter between the battery and the solar array. In this paper a parallel structure has been proposed which can improve the energy transfer efficiency and the battery charging time for satellite space power RPPT systems. An analogue controller is used to control all of the required functions, such as load voltage regulation and solar array stabilization with maximum power point tracking (MPPT). In order to compare the system efficiency and the battery charging efficiency of the proposed structure with those of a series (conventional) structure and a simplified series-parallel structure, simulations are performed and the results are analyzed using a loss analysis model. The proposed structure charges the battery more quickly when compared to the other two structures. Also the efficiency of the proposed structure has been improved under different modes of solar array operation when compared with the other two structures. To verify the system, experiments are carried out under different modes of solar array operation, including PPT charge, battery discharge, and eclipse and trickle charge.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.6
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• pp.533-541
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• 2011

This paper studies modeling of Jeju 80kV HVDC system and its controller by using PSCAD/EMTDC program. Reduced ac network is applied to verify interaction between ac network and dc system. Design parameter is applied to the converter transformer, harmonic filter and dc transmisstion line to simulate dc system. HVDC controller is divided into a rectifier controller and a inverter controller according to the converter operating mode. The inverter controller is composed of current control, voltage control and extingtion angle control. The rectifier controller is composed of current control and voltage control. Both controller has VDCOL characteristics so that current order is dependant on voltage variation. Step response, ac network single phase fault, three phase fault is simulated to verify the dynamic performance of controller model in both transient state and steady state.