• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.8
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• pp.24-33
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• 2002

For mixed signal circuits that integrate both analog and digital blocks onto the same chip, testing the mixed circuits has become the bottleneck. Since most of mixed signal circuits are functionally tested, mixed signal testing needs expensive automatic test equipments for test input generation and response acquisition. In this paper, a new efficient BIST is developed which can be used for mixed signal circuits. In the new BIST, only faults on embedded resistances, capacitances and its combinations are considered. To guarantee the quality of chips, the new BIST performs both voltage testing and phase testing. Using these two testing modes, all the faults are detected. In order to support this technique, the voltage detector and the phase detector are developed. Experimental results prove the efficiency of the new BIST.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.713-718
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• 2016

Predicting precise specifications of differential mixed-signal circuits is a difficult problem, because analytically derived correlation between process variations and conventional specifications exhibits the limited prediction accuracy due to the phase unbalance, for most self-tests. This paper proposes an efficient prediction technique to provide accurate specifications of differential mixed-signal circuits in a system-on-chip (SoC) based on a nonlinear statistical nonlinear regression technique. A spectrally pure sinusoidal signal is applied to a differential DUT, and its output is fed into another differential DUT through a weighting circuitry in the loopback configuration. The weighting circuitry, which is employed from the previous work [3], efficiently produces different weights on the harmonics of the loopback responses, i.e., the signatures. The correlation models, which map the signatures to the conventional specifications, are built based on the statistical nonlinear regression technique, in order to predict accurate nonlinearities of individual DUTs. In production testing, once the efficient signatures are measured, and plugged into the obtained correlation models, the harmonic coefficients of DUTs are readily identified. This work provides a practical test solution to overcome the serious test issue of differential mixed-signal circuits; the low accuracy of analytically derived model is much lower by the errors from the unbalance. Hardware measurement results showed less than 1.0 dB of the prediction error, validating that this approach can be used as production test.

• Journal of information and communication convergence engineering
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• v.14 no.4
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• pp.268-271
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• 2016

An efficient inductive switching noise suppression technique for mixed-signal integrated circuits (ICs) using standard CMOS digital technology is proposed. The proposed design technique uses a parallel RC circuit, which provides a damping path for the switching noise. The proposed design technique is used for designing a mixed-signal circuit composed of a ring oscillator, a digital output buffer, and an analog noise sensor node for $0.13-{\mu}m$ CMOS digital IC technology. Simulation results show a 47% reduction in the on-chip inductive switching noise coupling from the noisy digital to the analog blocks in the same substrate without an additional propagation delay. The increased power consumption due to the damping resistor is only 67% of that of the conventional source damping technique. This design can be widely used for any kind of analog and high frequency digital mixed-signal circuits in CMOS technology

• The Transactions of the Korea Information Processing Society
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• v.4 no.1
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• pp.311-323
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• 1997

This paper presents a fast fault simulation system for detecting stuck-at faults in mixed-level combinational logic circuits with gale level and switch -level primitives. For a practical fault simulator, the types are not restricted to static switch-level and/or gate-level circuits, but include dynamic switch-level circuits. To efficiently handle the multiple signal contention problems at wired logic elements, we propose a six-valued logic system and its logic calculus which are used together with signal strength information. As a basic algorithm for the fault simulation process, a well -known gate-level parallel pattern single fault propagation(PPSFP) technique is extended to switch-level circuits in order to handle pass-transistor circuits and precharged logic circuits as well as static CMOS circuits. Finally, we demonstrate the efficiency of our system through the experimental results for switch-level ISCAS85 benchmark combinational circuits and various industrial mixed-level circuits.

• ETRI Journal
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• v.30 no.4
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• pp.546-554
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• 2008

Phase-locked loops (PLLs) are among the most important mixed-signal building blocks of modern communication and control circuits, where they are used for frequency and phase synchronization, modulation, and demodulation as well as frequency synthesis. The growing popularity of PLLs has increased the need to test these devices during prototyping and production. The problem of distinguishing and classifying the responses of analog integrated circuits containing catastrophic faults has aroused recent interest. This is because most analog and mixed signal circuits are tested by their functionality, which is both time consuming and expensive. The problem is made more difficult when parametric variations are taken into account. Hence, statistical methods and techniques can be employed to automate fault classification. As a possible solution, we use the back propagation neural network (BPNN) to classify the faults in the designed charge-pump PLL. In order to classify the faults, the BPNN was trained with various training algorithms and their performance for the test structure was analyzed. The proposed method of fault classification gave fault coverage of 99.58%.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.847-850
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• 1998

One of the most difficult problem of designing VLSI is a mixed-circuit design, that is to design circuit containing both analog parts and digital parts. Digital to analog converter and analog to digital converter is a typical case. Especially it can be a serious problem when mixed circuit are put into a large digital circuit like microcontroller. However nowadays this problem is settled by separating analog circuit parts outside the IC. This technique is based on converting a digital signal into a pulse sequence. Then an analog signal is obtained by averaging this pulse sequence at the external low-pass filter. An anlog to digital converter is designed using a stochastic logic instead of a traditional PWM (pulse-width modulation) signal and ins implemente dusing FPGa. Stochastic pulse sequence can be made as a simple circuits and moreover can be mathematically processed by simple circuits -AND gates. The spectral property of stochastic pulse sequence method is better than that of PWM method. So it make easy to design a external low-pass filter. This technique has important advantages, especially the reduction of the ADC cost.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.3
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• pp.226-232
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• 2002

This paper explains a technique to improve the fault coverage of oscillation-test [1-5] for linear analog circuits. The transient behavior of the virtual ground is monitored during oscillation to extract information of the circuit. The limitation of the oscillation-test is analyzed, and an efficient signature analysis technique is proposed to maximize the fault coverage. The experimental result proves that the parametric fault coverage can be significantly increased by the proposed technique.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.149-152
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• 2002

The performance of a 1-bit DAC depends on that of the analog circuits. The mixed SC-CT (switched capacitor-continuous time) architecture is an effective design methodology for the analog circuits. This paper Proposes a new buffer scheme for the 1-bit digital-to-analog subconverter and a new SF-DSC(smoothing filter and differential-to-sig le converter) which performs both the smoothing filter and the differential-to-single convertor simultaneously.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.633-634
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• 2006

A new specification-based analog and mixed-signal test technique using high performance current sensors is proposed. The proposed technique using current sensors built in external ATE has little hardware overhead in circuit under test and high testability without time consuming operation of test point placement algorithm.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.901-904
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• 2005

Testing of mixed-signal circuit has become a difficult task for test engineers and efficient test solution to these problems are needed. In this paper a new specification-based mixed-signal test method called TSS(Time Slot Specification) using high performance current sensors and a novel test point selection technique without heavy computational overhead are proposed. External output and power nodes are used for test points and accessed by the current sensors in the ATE.