• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.100-101
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• 2012

The plasma damage free and room temperature processedthin film deposition technology is essential for realization of various next generation organic microelectronic devices such as flexible AMOLED display, flexible OLED lighting, and organic photovoltaic cells because characteristics of fragile organic materials in the plasma process and low glass transition temperatures (Tg) of polymer substrate. In case of directly deposition of metal oxide thin films (including transparent conductive oxide (TCO) and amorphous oxide semiconductor (AOS)) on the organic layers, plasma damages against to the organic materials is fatal. This damage is believed to be originated mainly from high energy energetic particles during the sputtering process such as negative oxygen ions, reflected neutrals by reflection of plasma background gas at the target surface, sputtered atoms, bulk plasma ions, and secondary electrons. To solve this problem, we developed the NBAS (Neutral Beam Assisted Sputtering) process as a plasma damage free and room temperature processed sputtering technology. As a result, electro-optical properties of NBAS processed ITO thin film showed resistivity of $4.0{\times}10^{-4}{\Omega}{\cdot}m$ and high transmittance (>90% at 550 nm) with nano- crystalline structure at room temperature process. Furthermore, in the experiment result of directly deposition of TCO top anode on the inverted structure OLED cell, it is verified that NBAS TCO deposition process does not damages to the underlying organic layers. In case of deposition of transparent conductive oxide (TCO) thin film on the plastic polymer substrate, the room temperature processed sputtering coating of high quality TCO thin film is required. During the sputtering process with higher density plasma, the energetic particles contribute self supplying of activation & crystallization energy without any additional heating and post-annealing and forminga high quality TCO thin film. However, negative oxygen ions which generated from sputteringtarget surface by electron attachment are accelerated to high energy by induced cathode self-bias. Thus the high energy negative oxygen ions can lead to critical physical bombardment damages to forming oxide thin film and this effect does not recover in room temperature process without post thermal annealing. To salve the inherent limitation of plasma sputtering, we have been developed the Magnetic Field Shielded Sputtering (MFSS) process as the high quality oxide thin film deposition process at room temperature. The MFSS process is effectively eliminate or suppress the negative oxygen ions bombardment damage by the plasma limiter which composed permanent magnet array. As a result, electro-optical properties of MFSS processed ITO thin film (resistivity $3.9{\times}10^{-4}{\Omega}{\cdot}cm$, transmittance 95% at 550 nm) have approachedthose of a high temperature DC magnetron sputtering (DMS) ITO thin film were. Also, AOS (a-IGZO) TFTs fabricated by MFSS process without higher temperature post annealing showed very comparable electrical performance with those by DMS process with $400^{\circ}C$ post annealing. They are important to note that the bombardment of a negative oxygen ion which is accelerated by dc self-bias during rf sputtering could degrade the electrical performance of ITO electrodes and a-IGZO TFTs. Finally, we found that reduction of damage from the high energy negative oxygen ions bombardment drives improvement of crystalline structure in the ITO thin film and suppression of the sub-gab states in a-IGZO semiconductor thin film. For realization of organic flexible electronic devices based on plastic substrates, gas barrier coatings are required to prevent the permeation of water and oxygen because organic materials are highly susceptible to water and oxygen. In particular, high efficiency flexible AMOLEDs needs an extremely low water vapor transition rate (WVTR) of $1{\times}10^{-6}gm^{-2}day^{-1}$. The key factor in high quality inorganic gas barrier formation for achieving the very low WVTR required (under ${\sim}10^{-6}gm^{-2}day^{-1}$) is the suppression of nano-sized defect sites and gas diffusion pathways among the grain boundaries. For formation of high quality single inorganic gas barrier layer, we developed high density nano-structured Al2O3 single gas barrier layer usinga NBAS process. The NBAS process can continuously change crystalline structures from an amorphous phase to a nano- crystalline phase with various grain sizes in a single inorganic thin film. As a result, the water vapor transmission rates (WVTR) of the NBAS processed $Al_2O_3$ gas barrier film have improved order of magnitude compared with that of conventional $Al_2O_3$ layers made by the RF magnetron sputteringprocess under the same sputtering conditions; the WVTR of the NBAS processed $Al_2O_3$ gas barrier film was about $5{\times}10^{-6}g/m^2/day$ by just single layer.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권5호
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• pp.657-663
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• 2016

In this work, a novel silicon (Si) based floating body synaptic transistor (SFST) is studied to mimic the transition from short-term memory to long-term one in the biological system. The structure of the proposed SFST is based on an n-type metal-oxide-semiconductor field-effect transistor (MOSFET) with floating body and charge storage layer which provide the functions of short- and long-term memories, respectively. It has very similar characteristics with those of the biological memory system in the sense that the transition between short- and long-term memories is performed by the repetitive learning. Spike timing-dependent plasticity (STDP) characteristics are closely investigated for the SFST device. It has been found from the simulation results that the connectivity between pre- and post-synaptic neurons has strong dependence on the relative spike timing among electrical signals. In addition, the neuromorphic system having direct connection between the SFST devices and neuron circuits are designed.

• 한국전기전자재료학회논문지
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• 제27권6호
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• pp.356-360
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• 2014

In this paper, the effect of underpass structure on quality factor and breakdown voltage of octagonal inductors which were fabricated with 90 nm complementary metal-oxide-semiconductor (CMOS) technology for radio frequency integrated circuit (RFIC) was studied. It was found that quality factor and breakdown voltage of inductors with more than one metal layer for underpass showed improved properties compared to those with one metal layer. However, little change of quality factor and breakdown voltage was observed between the inductors with two and more than two metal layers for underpass. Therefore, underpasses with two metal layers are promising for RFIC designs of the octagonal inductors in 90 nm CMOS technology.

• Current Optics and Photonics
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• 제7권5호
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• pp.485-495
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• 2023

The pixel size in high-resolution complementary metal-oxide-semiconductor (CMOS) image sensors continues to shrink due to chip size limitations. However, the pixel pitch's miniaturization causes deterioration of optical performance. As one solution, a quad color filter (CF) array with pixel binning has been developed to enhance sensitivity. For high sensitivity, the microlens structure also needs to be optimized as the CF arrays change. In this paper, the covered microlens, which consist of four microlenses covered by one large microlens, are proposed for the quad CF array in the backside illumination pixel structure. To evaluate the optical performance, the suggested microlens structure was simulated from 0.5 ㎛ to 1.0 ㎛ pixels at the center and edge of the sensors. Moreover, all pixel structures were compared with and without in-pixel deep trench isolation (DTI), which works to distribute incident light uniformly into each photodiode. The suggested structure was evaluated with an optical simulation using the finite-difference time-domain method for numerical analysis of the optical characteristics. Compared to the conventional microlens, the suggested microlens show 29.1% and 33.9% maximum enhancement of sensitivity at the center and edge of the sensor, respectively. Therefore, the covered microlens demonstrated the highly sensitive image sensor with a quad CF array.

• 한국표면공학회지
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• 제29권6호
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• pp.809-815
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• 1996

$Y_2O_3$-based metal-insulator-semiconductor (MIS) structure on p-Si(100) has been studied. Films were prepared by UHV reactive ionized cluster beam deposition (r-ICBD) system. The base pressure of the system was about $1 \times 10^{-9}$ -9/ Torr and the process pressure $2 \times 10^{-5}$ Torr in oxygen ambience. Glancing X-ray diffraction(GXRD) and in-situ reflection high energy electron diffracton(RHEED) analyses were performed to investigate the crystallinity of the films. The results show phase change from amorphous state to crystalline one with increasingqr acceleration voltage and substrate temperature. It is also found that the phase transformation from $Y_2O_3$(111)//Si(100) to $Y_2O_3$(110)//Si(100) in growing directions takes place between $500^{\circ}C$ and $700^{\circ}C$. Especially as acceleration voltage is increased, preferentially oriented crystallinity was increased. Finally under the condition of above substrate temperature $700^{\circ}C$ and acceleration voltage 5kV, the $Y_2O_3$films are found to be grown epitaxially in direction of $Y_2O_3$(1l0)//Si(100) by observation of transmission electron microscope(TEM). Capacitance-voltage and current-voltage measurements were conducted to characterize Al/$Y_2O_3$/Si MIS structure with varying acceleration voltage and substrate temperature. Deposited $Y_2O_3$ films of thickness of nearly 300$\AA$ show that the breakdown field increases to 7~8MV /cm at the same conditon of epitaxial growing. These results also coincide with XPS spectra which indicate better stoichiometric characteristic in the condition of better crystalline one. After oxidation the breakdown field increases to 13MV /cm because the MIS structure contains interface silicon oxide of about 30$\AA$. In this case the dielectric constant of only $Y_2O_3$ layer is found to be $\in$15.6. These results have demonstrated the potential of using yttrium oxide for future VLSI/ULSI gate insulator applications.

• 센서학회지
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• 제24권2호
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• pp.131-136
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• 2015

This paper presents a wide dynamic range complementary metal oxide semiconductor (CMOS) image sensor with column capacitor and feedback structure. The designed circuit has been fabricated by using $0.18{\mu}m$ 1-poly 6-metal standard CMOS technology. This sensor has dual mode operation using combination of active pixel sensor (APS) and passive pixel sensor (PPS) structure. The proposed pixel operates in the APS mode for high-sensitivity in normal light intensity, while it operates in the PPS mode for low-sensitivity in high light intensity. The proposed PPS structure is consisted of a conventional PPS with column capacitor and feedback structure. The capacitance of column capacitor is changed by controlling the reference voltage using feedback structure. By using the proposed structure, it is possible to store more electric charge, which results in a wider dynamic range. The simulation and measurement results demonstrate wide dynamic range feature of the proposed PPS.

• 대한전자공학회논문지SD
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• 제39권5호
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• pp.1-7
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• 2002

Deep sub-micron bulk CMOS circuits require gate electrode materials such as metal silicide and titanium silicide for gate oxides. Many authors have conducted research to improve the quality of the sub-micron gate oxide. However, few have reported on the electrical quality and reliability of an ultra-thin gate. In this paper, we will recommend a novel shallow trench isolation structure and a two-step TiS $i_2$ formation process to improve the corner metal oxide semiconductor field-effect transistor (MOSFET) for sub-0.1${\mu}{\textrm}{m}$ VLSI devices. Differently from using normal LOCOS technology, deep sub-micron CMOS devices using the novel shallow trench isolation (STI) technology have unique "inverse narrow-channel effects" when the channel width of the device is scaled down. The titanium silicide process has problems because fluorine contamination caused by the gate sidewall etching inhibits the silicide reaction and accelerates agglomeration. To resolve these Problems, we developed a novel two-step deposited silicide process. The key point of this process is the deposition and subsequent removal of titanium before the titanium silicide process. It was found by using focused ion beam transmission electron microscopy that the STI structure improved the narrow channel effect and reduced the junction leakage current and threshold voltage at the edge of the channel. In terms of transistor characteristics, we also obtained a low gate voltage variation and a low trap density, saturation current, some more to be large transconductance at the channel for sub-0.1${\mu}{\textrm}{m}$ VLSI devices.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.287.1-287.1
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• 2016

Three-dimensional (3-D) semiconductor nanoarchitectures, including nano- and micro- rods, pyramids, and disks, are emerging as one of the most promising elements for future optoelectronic devices. Since these 3-D semiconductor nanoarchitectures have many interesting unconventional properties, including the use of large light-emitting surface area and semipolar/nonpolar nano- or micro-facets, numerous studies reported on novel device applications of these 3-D nanoarchitectures. In particular, 3-D nanoarchitecture devices can have noticeably different current spreading characteristics compared with conventional thin film devices, due to their elaborate 3-D geometry. Utilizing this feature in a highly controlled manner, color-tunable light-emitting diodes (LEDs) were demonstrated by controlling the spatial distribution of current density over the multifaceted GaN LEDs. Meanwhile, for the fabrication of high brightness, single color emitting LEDs or laser diodes, uniform and high density of electrical current must be injected into the entire active layers of the nanoarchitecture devices. Here, we report on a new device structure to inject uniform and high density of electrical current through the 3-D semiconductor nanoarchitecture LEDs using metal core inside microtube LEDs. In this work, we report the fabrications and characteristics of metal-cored coaxial $GaN/In_xGa_{1-x}N$ microtube LEDs. For the fabrication of metal-cored microtube LEDs, $GaN/In_xGa_{1-x}N/ZnO$ coaxial microtube LED arrays grown on an n-GaN/c-Al2O3 substrate were lifted-off from the substrate by wet chemical etching of sacrificial ZnO microtubes and $SiO_2$ layer. The chemically lifted-off layer of LEDs were then stamped upside down on another supporting substrates. Subsequently, Ti/Au and indium tin oxide were deposited on the inner shells of microtubes, forming n-type electrodes of the metal-cored LEDs. The device characteristics were investigated measuring electroluminescence and current-voltage characteristic curves and analyzed by computational modeling of current spreading characteristics.

• 한국전기전자재료학회논문지
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• 제26권4호
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• pp.284-288
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• 2013

Power MOSFETs(Metal Oxide Semiconductor Field Effect Transistor) operate as energy control semiconductor switches. In order to reduce energy loss of the device during switch-on state, it is essential to increase its conductance. We have experimental results and explanations on the doping profile dependence of the electrical behavior of the vertical MOSFET. The device is fabricated as $8.25{\mu}m$ cell pitch and $4.25{\mu}m$ gate width. The performances of device with various p base doping concentration are compared at Vth from 1.77 V to 4.13 V. Also the effect of the cell structure on the on-resistance and breakdown voltage of the device are analyzed. The simulation results suggest that the device optimized for various applications can be further optimized at power device.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.854-859
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• 2016

Recently, GeSn is drawing great deal of interests as one of the candidates for group-IV-driven optical interconnect for integration with the Si complementary metal-oxide-semiconductor (CMOS) owing to its pseudo-direct band structure and high electron and hole mobilities. However, the large lattice mismatch between GeSn and Si as well as the Sn segregation have been considered to be issues in preparing GeSn on Si. In this work, we deposit the GeSn films on Si by DC magnetron sputtering at a low temperature of $250^{\circ}C$ and characterize the thin films. To reduce the stresses by GeSn onto Si, Ge buffer deposited under different processing conditions were inserted between Si and GeSn. As the result, polycrystalline GeSn domains with Sn atomic fraction of 6.51% on Si were successfully obtained and it has been demonstrated that the Ge buffer layer deposited at a higher sputtering power can relax the stress induced by the large lattice mismatch between Si substrate and GeSn thin films.